Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Initialization
Data Sheet
could not use the busy bit to determine when to start a
new write, but would need to insert a delay (deter-
mined by the “shut down” time of the nvRAM, between
5-10 ms). Fortunately, the S5320 implements the
Acknowledge Polling scheme described above, which
will not take away the busy bit until the write is truly fin-
ished, and the external nvRAM is available for
accesses.
the read data in RCR(32:16) may not be valid.
This flag remains set until the start of the next
read/write operation.
When performing a word/double-word RCR
access, you can combine the data and control in
the same command. The following is the sequence
for a write:
1. Verify that busy bit, RCR(31), is not set by read-
ing RCR(31). If set, hold off starting the write
sequence (repeat step 1 until the bit clears).
The following sequence is used to perform nvRAM
writes when accessing the RCR/ARCR in a byte-
wide fashion:
2. Write to RCR(31:29) = “100” and RCR(23:16)
with the low address byte. This will directly load
NVRAM_LOW_ADDR with RCR(23:16).
1. Verify that busy bit, RCR(31), is not set by read-
ing RCR(31). If set, hold off starting the read
sequence (repeat step 1 until this bit clears).
3. Write to RCR(31:29) = “101” and RCR(23:16)
with the high address byte. This will directly load
NVRAM_HIGH_ADDR with RCR(23:16).
2. Write to RCR(31:29) = “100”, the command to
load the low address byte. This will assert the
internal signal LOAD_LOW_ADDR, which is used
to enable the loading of the low-address register
(NVRAM_LOW_ADDR).
4. Write to RCR(31:29) = “110” and RCR(23:16)
with the write data. This will directly load the write
data register with RCR(23:16). This will also set
the busy bit, RCR(31). The nvRAM interface con-
troller will now initiate a write operation to the
external nvRAM.
3. Write to RCR(23:16) with the low address byte.
Since signal LOAD_LOW_ADDR is asserted, the
data will be written to the register
NVRAM_LOW_ADDR.
As
long
as
5. Poll the busy bit until it is no longer set. Once
cleared, it is now safe to perform another write/
read operation to the external nvRAM. In addi-
tion, evaluate the XFER_FAIL flag (bit 28) to
determine whether the transfer was successful or
not. If XFER_FAIL is asserted, this indicates that
a transfer to the nvRAM did not receive an
ACKNOWLEDGE. The write should not be con-
sidered successful. This flag remains set until the
start of the next read/write operation.
LOAD_LOW_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_LOW_ADDR.
4. Write to RCR(31:29) = “101”, the command to
load the high address byte. This will assert the
internal signal LOAD_HIGH_ADDR, which is
used to enable the loading of the high-address
register (NVRAM_HIGH_ADDR).
5. Write to RCR(23:16) with the high address byte.
Since signal LOAD_HIGH_ADDR is asserted, the
data will be written to the register
NVRAM_HIGH_ADDR. Note that as the nvRAM
address is limited to 11-bits, only the 3-lsb’s of
this write data is actually used. As long as
LOAD_HIGH_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_HIGH_ADDR.
The following sequence is used for a read:
1. Verify that the busy bit, RCR(31), is not set by
reading RCR(31). If set, hold off starting the read
sequence (repeat step 1 until the bit clears).
2. Write to RCR(31:29) = “100” and RCR(23:16)
with the low address byte. This will directly load
NVRAM_LOW_ADDR with RCR(23:16).
6. Write to RCR(31:29) = “111”, the command to
start the nvRAM read operation. This will set the
busy bit, RCR(31). The nvRAM interface control-
ler will now initiate a read operation to the
external nvRAM.
3. Write to RCR(31:29) = “101” and RCR(23:16)
with the high address byte. This will directly load
NVRAM_HIGH_ADDR with RCR(23:16).
4. Write to RCR(31:29) = “111”. This will set the
busy bit, RCR(31). The nvRAM interface control-
ler will now initiate a read operation with the
external nvRAM.
7. Poll the busy bit until it is no longer set. Once
cleared, the read data will be located in
RCR(23:16). In addition, evaluate the
XFER_FAIL flag (bit 28) to determine whether the
transfer was successful or not. If XFER_FAIL is
asserted, this indicates that a transfer to the
nvRAM did not receive an ACKNOWLEDGE, and
5. Poll the busy bit until it is no longer set. Once
cleared, the read data will be located in
RCR(23:16). In addition, evaluate the
XFER_FAIL flag (bit 28) to determine whether the
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