Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Initialization
Data Sheet
NOT perform two-wire serial arbitration. It assumes
that it is the only master on the bus.
of the S5320, this corresponds to one byte of data
transferred approximately every 0.25 milliseconds.
Read accesses can be either random or sequential.
During boot-up, all accesses from address 40h to 7Fh
are sequential. As a result, it is important the nvRAM
used supports the nvRAM sequential read accesses
as indicated in Figure 40. Figure 39 shows the
sequence for a random byte read.
Communications with the serial memory involve sev-
eral clock transitions. A start event signals the
beginning of a transaction and is immediately followed
by an address transfer. Each address/data transfer
consists of 8 bits of information followed by a 1-bit
acknowledgment. When the exchange is complete, a
stop event is issued. Figure 36 shows the unique rela-
tionship defining both a start and stop event. Figure 37
shows the required timing for address/data with
respect to the serial clock.
To initialize the S5320 controller’s PCI Configuration
Registers, the smallest serial device necessary is a
128 x 8 organization. Although the S5320 controller
only requires 64 bytes, these configuration bytes must
begin at the 64-byte address offset (40h through 7Fh).
This offset constraint permits the configuration image
to be shared with a memory containing expansion
BIOS code and the necessary preamble to identify an
expansion BIOS. The largest serial device which can
be used is 2 Kbytes.
For random accesses, the sequence involves one
clock to define the start of the sequence, eight clocks
to send the slave address and read/write command,
followed by a one-clock acknowledge, and so on. Fig-
ure 38 shows the sequence for a random write access
requiring 29 serial clock transitions. At the clock speed
Table 38. Valid External Boot Memory Contents
Address
Data
Notes
0040h-0041h
not FFFFh
This is the location that the S5320 will load a customized vendor ID. (FFFFh is an
illegal vendor ID.)
0050h
82h - registers to I/O
81h - memory space
80h - memory below
1 Mbytes
This is the least significant byte of the region which initializes the S5320 configura-
tion register BADR0. A value of 81h assigns the 32 DWORD locations of the PCI
operations registers into I/O space, a value of 80h defines memory space, and a
value of 82h defines memory space below 1 Mbytes.
0051h
0052h
0053h
FFh
E8h
10h
Required
Required
Required
80
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