Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Initialization
INITIALIZATION
Data Sheet
LOADING THE SERIAL NV MEMORY
All PCI bus agents and bridges are required to imple-
ment PCI Configuration Registers. When multiple PCI
devices are present, these registers must be unique to
each device in the system. The specified PCI proce-
dure for uniquely selecting a device’s configuration
space involves a dedicated signal, called IDSEL, con-
nected to each motherboard PCI bus device and PCI
slot.
Serial nv memory data transfers are performed
through a two-wire, bi-directional data transfer protocol
as defined by commercial serial EEPROM offerings.
These devices have the advantages of low pin counts,
small package size, and economical price.
A serial nv memory is initially considered valid if the
first serial accesses contain the correct per-byte
acknowledgments (see Figure 39. If the serial per-byte
acknowledgment is not observed, the S5320 deter-
mines that no external serial nv memory is present
and the AMCC default Configuration Register values
specified in the PCI Configuration Register Chapter
are used. Please note that the Pass-Thru interface will
not operate unless a valid nv memory has been read.
After reset, the host executes configuration cycles to
each device on the PCI bus. The configuration regis-
ters provide information on PCI agent operation and
memory or I/O space requirements. These allow the
PCI BIOS to enable the device and locate it within sys-
tem memory or I/O space.
After a PCI reset, the S5320 can be configured for a
specific application by downloading device setup infor-
mation from an external non-volatile memory into the
device Configuration Registers. In order to use the
Pass-Thru regions, the S5320 must be used with an
external nvRAM boot device If no nvRAM is used, the
Base-Address Regions are disabled. However, the
mailboxes and other PCI/Add-on Operation Registers
can still be used (as Base-Address Region #0 comes
up in its default state, defining a 128-byte I/O region).
The serial nvRAM is first accessed at location 0040h
followed by a read to location 0041h. If either of these
accesses contain anything other than FFh, the next
four accesses are to locations 0050h, 0051h, 0052h
and 0053h. At these locations, the data must be 80h
(or 81h or 82h), FFh, E8h, and 10h, respectively, for
the external nv memory to be considered valid. Once a
valid external nv memory has been recognized, it is
read, sequentially from location 040h to 07Fh. The
data is loaded into the appropriate PCI configuration
register. Some of the boot device data is not down-
loaded into the Configuration Registers, but is used
instead to initialize some S5320 modes of operation
(location 0045h, for instance). Upon completion of this
sequence, the boot load terminates and PCI configu-
ration accesses to the S5320 are acknowledged with
the PCI Target Ready (TRDY#) output.
To configure the S5320, 64 bytes of setup information
are required. The rest of the boot device can be used
to implement an expansion BIOS, if desired. Some of
the setup information is used to initialize the S5320
PCI Configuration Registers, while other information is
used to define S5320 special operating modes.
PCI RESET
Table 38 lists the required nv memory contents for a
valid configuration nv memory device.
Immediately following the assertion of the PCI RST#
signal, the Add-On reset output SYSRST# is asserted.
The Add-On reset output (SYSRST#) can be used to
initialize external state machines, reset Add-On micro-
processors, or other Add-On logic devices.
Two pins are used to transfer data between the S5320
PCI controller and the external serial memory: a serial
clock pin, SCL, and a serial data pin, SDA. The serial
clock pin is an open drain output from the S5320, and
the serial data pin is open drain bi-directional. The
serial clock is derived by dividing the PCI bus clock by
293. This means the frequency of the serial clock is
approximately 114 KHz for a 33 MHz PCI bus clock.
All S5320 Operation Registers and Configuration Reg-
isters are initialized to their default states at reset. The
default values for the Configuration Registers will be
overwritten by the contents of the external nv boot
memory during device initialization. Configuration
accesses by the host CPU while the S5320 is loading
configuration will produce PCI bus retries until one of
the following events occurs:
Note in Figure 35, a 4.7k pull-up is required on the
SDA and SCL lines. During boot-up, the S5320 will
only communicate with an EEPROM that has its
address pins set to 0 (A[2:0] = “000). When not
accessing the external nvRAM, the S5320 will tri-state
the SCL and SDA signals so other two-wire serial
devices can use the bus. The system designer must
guarantee that the two-wire serial bus is idle whenever
the S5320 wants to start an access. The S5320 does
•
The S5320 identifies that there is no valid boot
memory (and default Configuration Register
values are used).
•
The S5320 finishes downloading all configura-
tion information from a valid boot memory.
AMCC Confidential and Proprietary
DS1656
79
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
