Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker
Data Sheet
TABLE OF CONTENTS
Reading an Add-On Incoming Mailbox: ......................................................................................................... 104
Writing an Add-On Outgoing Mailbox: ........................................................................................................... 104
Mailbox Interrupts .......................................................................................................................................... 105
Servicing a PCI Mailbox Interrupt (INTA# Asserted): .................................................................................... 106
Servicing the Add-On mailbox interrupt (IRQ# Asserted): ............................................................................. 106
ADD-ON LOCAL BUS INTERFACE ................................................................................................................... 108
ADD-ON INTERFACE SIGNALS ........................................................................................................................ 108
SYSTEM SIGNALS ............................................................................................................................................. 108
ADD-ON S5320 REGISTER ACCESSES ........................................................................................................... 108
Register Access Signals ................................................................................................................................ 108
S5320 General Register Accesses ................................................................................................................ 108
S5320 16-bit Mode Register Accesses ......................................................................................................... 109
MAILBOX OVERVIEW ........................................................................................................................................ 111
PASS-THRU OVERVIEW .................................................................................................................................... 111
WRITE FIFO OVERVIEW .................................................................................................................................... 111
READ FIFO OVERVIEW ..................................................................................................................................... 111
FUNCTIONAL DESCRIPTION ............................................................................................................................ 111
Pass-Thru Transfers ...................................................................................................................................... 111
Pass-Thru Status/Control Signals ................................................................................................................. 112
BUS INTERFACE ................................................................................................................................................ 112
PCI Bus Interface .......................................................................................................................................... 112
PCI Pass-Thru Single Cycle Accesses .......................................................................................................... 113
PCI Pass-Thru Burst Accesses ..................................................................................................................... 113
PCI Disconnect Conditions ............................................................................................................................ 113
PCI Write Disconnect .................................................................................................................................... 114
PCI Read Disconnect .................................................................................................................................... 114
S5320 PASSIVE MODE OPERATION ................................................................................................................ 115
Single-Cycle PCI to Pass-Thru Write ............................................................................................................ 115
Single-Cycle PCI to Pass-Thru Read ............................................................................................................ 116
PCI to Pass-Thru Burst Writes ...................................................................................................................... 117
Pass-Thru Burst Reads ................................................................................................................................. 122
Using PTRDY# to assert Wait-States ............................................................................................................ 123
8-Bit and 16-Bit Pass-Thru Add-On Bus Interface in Passive Mode ............................................................. 124
Endian Conversion ........................................................................................................................................ 128
Active Operation ............................................................................................................................................ 128
Active mode Programmable Wait States ....................................................................................................... 131
PTRDY#/PTWAIT# ........................................................................................................................................ 131
DXFR# ........................................................................................................................................................... 132
Active Mode Figures and Descriptions .......................................................................................................... 132
Active mode Burst cycles .............................................................................................................................. 132
Clock by Clock description of Figure 75 ........................................................................................................ 133
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