Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker
Data Sheet
LIST OF FIGURES
Figure 38. Serial Interface Byte Access-Write ....................................................................................................... 82
Figure 39. Serial Interface Byte Access-Read ....................................................................................................... 82
Figure 40. Serial Byte Access- Sequential Read ................................................................................................... 82
Figure 41. PCI AD Bus Definition Type 0 Configuration Access ............................................................................ 86
Figure 42. Type 0 Configuration Read Cycles ....................................................................................................... 86
Figure 43. Type 0 Configuration Write Cycles ....................................................................................................... 87
Figure 44. Single Data Phase PCI Bus Read of S5320 Registers or Expansion ROM ......................................... 93
Figure 45. Burst PCI Bus Read Attempt to S5320 Registers or Expansion ROM ................................................. 94
Figure 46. Burst PCI Bus Write of S5320 Registers .............................................................................................. 94
Figure 47. Target Disconnect Example 1 ............................................................................................................... 94
Figure 48. Target Disconnect Example 2 ............................................................................................................... 95
Figure 49. Target-Initiated Retry ............................................................................................................................ 95
Figure 50. Engaging the LOCK# Signal ................................................................................................................. 96
Figure 51. Access to a Locked Target by its Owner .............................................................................................. 98
Figure 52. Access Attempt to a Locked Target ...................................................................................................... 98
Figure 53. Error Reporting Signal .......................................................................................................................... 98
Figure 54. PCI to Add-On Mailbox Register ......................................................................................................... 100
Figure 55. Add-On to PCI Mailbox Register ......................................................................................................... 101
Figure 56. Input/Output Mode (MDMODE=0) ...................................................................................................... 103
Figure 57. Input Mode (MDMODE=1) .................................................................................................................. 103
Figure 58. Read Operation Register .................................................................................................................... 109
Figure 59. Write Operation Register .................................................................................................................... 109
Figure 60. 16 Bit Mode Operation Register DWORD Write/Read ........................................................................ 110
Figure 61. PCI To Add-On Passive Write ............................................................................................................ 116
Figure 62. PCI To Add-On Passive Write w/Pass-Thru Address ......................................................................... 116
Figure 63. PCI To Add-On Passive Read ............................................................................................................ 117
Figure 64. PCI to Add-On Passive Burst Write .................................................................................................... 118
Figure 65. PCI to Add-On Passive Burst Write Using PTRDY# to assert Wait-States ........................................ 120
Figure 66. PCI to Add-On Passive Burst Read Access ....................................................................................... 120
Figure 67. PCI to Add-On Passive Burst Read .................................................................................................... 122
Figure 68. PCI to Add-On Passive Write to an 8-bit ............................................................................................ 127
Figure 69. PCI to Add-On Passive Read to an 16-bit Add-On Device ................................................................. 129
Figure 70. Active mode PCI Read (Zero Programmed Wait States) with PTADR# ............................................. 130
Figure 71. Active Mode PCI Read without PTADR# ............................................................................................ 130
Figure 72. Active Mode PCI Write without PTADR# ............................................................................................ 130
Figure 73. Active Mode PCI Write with Add-On Initiated Wait States Using PTWAIT# ....................................... 131
Figure 74. Active Mode 32-Bit PCI Write ............................................................................................................. 131
10
DS1656
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
