Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
Figure 17. Base Address Register - I/O
0
1
Bit
31
2
1
0
Value
Base Address
I/O Space
Indicator (RO)
Reserved (RO)
Programmable (R/W)
Bit
Description
31:2
Base Address Location. These bits are used to position the decoded region in I/O space. Only bits which return
a 1 after being written as 1 are usable for this purpose. Except for Base Address 0, these bits are individually
enabled by the contents sourced from the external nvRAM.
1
0
Reserved. This bit should be 0. (Note: disabled Base Address Registers will return all 0s for the entire register
location, bits 31 through 0).
Space Indicator = 1. When 1, this bit identifies a base address region as an I/O space and the remaining bits in
the base address register have the definition as shown in Figure 17.
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