Revision 1.08 – October 15, 2007
440GRx – PPC440GRx Embedded Processor
DDR2/1 SDRAM I/O Specifications
Preliminary Data Sheet
The DDR2/1 SDRAM controller times its operation with the internal PLB clock signal and generates MemClkOut
from the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut is
the same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Read capture logic in the DDR controller captures read data using a delayed version of DQS and internally re-
synchronizes the data to the PLB clock.The PPC440GRx contains three independently programmable digital delay
lines (DLLs) that control the timing of the indicated signals in read and write operations:
1. DQS (with respect to MemClkOut) for write operations.
2. MemData, ECC, and DM (with respect to MemClkOut) for write operations.
3. DQS (with respect to inbound MemData) for read operations.
There is also a master delay line for calibration. Programming details can be found in the PPC440GRx Embedded
Processor Users Manual.
The signals are terminated as indicated in Figure 10 for the DDR timing data in the following sections.
The PPC440GRx uses a clock forwarding scheme in which it drives the clock to the memory devices.
Data signals are divided into eight subgroups—one for each byte lane (see Table 27 on page 85)— plus a ninth
subgroup for the ECC byte lane. These signals include MemData00:63, DQS0:8, DM0:8, and ECC0:7 signals.
Signals within a data subgroup (byte lane) should be routed together.
Command Bus Operation
The command bus (MemAddr, RAS, CAS, WE, BA, ClkEn, BankSel, MemODT) is driven 180° out-of-phase with
MemClkOut, and has no corresponding delay line. Therefore, board designers must consider two different types of
systems: 1) registered DIMMs and 2) unbuffered DIMMs. The system clocking design must also be considered. To
avoid crosstalk, the command bus signals and the data signals should not be routed together.
Board Layout Restrictions
The paths (traces) for the data and the associated data strobe signal should be routed with the same length
between the PPC440GRx and the SDRAM devices, allowing the rising and falling edges of the strobe to arrive at
the capture logic at the same time the data is in transition. All of the following timing assumes a trace velocity of
167ps/in.
Board designs must meet the following criteria:
• Skew on the signals in any byte lane should not exceed 50ps (0.3 in).
• Data subgroup trace lengths must be no more than 5in. (800ps) and have a difference of no more than 2.5in.
(400ps).
• Byte lane subgroup trace length must be no less than 1.25in. (209ps).
For example, traces that average 3.00in. in length and 167ps/in., and meet the maximum 50ps skew requirement,
would have a maximum length difference of 0.3in. So, they would be between 2.85in. and 3.15in. in length.
If the above timing recommendations are followed, the package wire bond lengths can be ignored.
Clocking
Clocking skew to all DRAMs must be minimized. The maximum allowed is considered to be 10ps. Because of the
stringent requirements on DDR device clock inputs, it is expected that board designers will use some type of
external PLL suitable to redrive the clock to the DDR SDRAMs. In such a system, the PLL acts like a zero-delay
insertion buffer.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
