Revision 1.08 – October 15, 2007
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
Table 23. DDR SDRAM Output Driver Specifications (Sheet 2 of 2)
Output Current (mA)
Signal Path
I/O H (maximum)
I/O L (maximum)
RAS
10
10
10
10
10
10
10
10
10
10
10
10
10
10
CAS
WE
BankSel0:1
ClkEn
DQS0:8
MemODT0:1
DDR SDRAM Write Operation
The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes. The following data is
generated by means of simulation and includes logic, driver, package RLC, and lengths. Values are calculated
over best case and worst case processes with speed, junction temperature, and voltage as follows:
Table 24. DDR SDRAM Write Operation Conditions
Case
Best
Process Speed
Fast
Junction Temperature (°C)
Voltage (V)
+1.6
−40
Worst
Slow
+125
+1.425
Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and
maximum values are measured under worst case conditions. The timing numbers in the following sections are
obtained using a simulation that assumes a model as shown in Figure 10, DDR SDRAM Simulation Signal
Termination Model.
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