Revision 1.08 – October 15, 2007
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
Figure 8. Input Setup and Hold Waveform for RGMII Signals
GMCnRxClk
1.25V
T
T
min
min
IH
IS
T
T
min
min
IH
IS
Inputs
Valid
Valid
RGMII 1000Mb timing is with reference to the raising and falling edge of GMCnRxClk.
RGMII 10/100Mb timing is with reference only to the raising edge of GMCnRxClk.
Figure 9. Output Delay and Hold Timing Waveform for RGMII Signals
GMCnTxClk
1.25V
min
T
min
T
OH
OH
T
max
T
Outputs
max
OV
OV
High (Drive)
Float (High-Z)
Valid
Valid
Valid
Valid
Low (Drive)
RGMII 1000Mb timing is with reference to the raising and falling edge of GMCnTxClk.
RGMII 10/100Mb timing is with reference only to the raising edge of GMCnTxClk.
AMCC Proprietary
75
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
