Revision 1.08 – October 15, 2007
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
I/O Specifications
Table 20. Peripheral Interface Clock Timings
Parameter
PCIClk frequency (asynchronous mode)
PCIClk period (asynchronous mode)
PCIClk high time
Min
Max
Units
MHz
ns
Notes
–
66.66
15
–
40% of nominal period
60% of nominal period
ns
PCIClk low time
40% of nominal period
60% of nominal period
ns
GMCMDClk frequency
GMCMDClk period
–
2.5
MHz
ns
400
–
GMCMDClk high time
GMCMDClk low time
160
–
ns
160
–
ns
GMCTxClk frequency MII
GMCTxClk period MII
GMCTxClk high time
2.5
25
MHz
ns
40
400
35% of nominal period
–
ns
GMCTxClk low time
35% of nominal period
–
ns
GMCRxClk frequency MII
GMCRxClk period MII
GMCRxClk high time
2.5
25
MHz
ns
40
400
35% of nominal period
35% of nominal period
–
–
ns
GMCRxClk low time
–
ns
GMCRefClk frequency
GMCRefClk period
125
MHz
MHz
ns
8
–
GMCRefClk high time
GMCRefClk low time
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
2
2
ns
PerClk (and OPB Clock) frequency (for ext. master or sync.
slaves)
33.33MHz
83.33
MHz
GMCRefClk Edge stability (cycle-to-cycle jitter)
GMCRefClk Slew Rate
PerClk period
–
+0.15
ns
V/ns
ns
2
–
12
30
PerClk high time
50% of nominal period
33% of nominal period
66% of nominal period
50% of nominal period
ns
PerClk low time
ns
1000 / (2TOPB1+2ns)
UARTSerClk frequency
UARTSerClk period
–
MHz
ns
1
1
1
1
2TOPB1+2
TOPB1+1
TOPB1+1
–
–
–
UARTSerClk high time
UARTSerClk low time
ns
ns
AMCC Proprietary
73
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
