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EPM7256AEFC256-10 参数 Datasheet PDF下载

EPM7256AEFC256-10图片预览
型号: EPM7256AEFC256-10
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 10ns, 256-Cell, CMOS, PBGA256, FINE LINE, BGA-256]
分类和应用: 时钟LTE输入元件可编程逻辑
文件页数/大小: 64 页 / 437 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 7000A Programmable Logic Device Data Sheet  
The MAX 7000A architecture includes the following elements:  
Functional  
Description  
Logic array blocks (LABs)  
Macrocells  
Expander product terms (shareable and parallel)  
Programmable interconnect array  
I/O control blocks  
The MAX 7000A architecture includes four dedicated inputs that can be  
used as general-purpose inputs or as high-speed, global control signals  
(clock, clear, and two output enable signals) for each macrocell and I/O  
pin. Figure 1 shows the architecture of MAX 7000A devices.  
6
Altera Corporation