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EPM7256AEFC256-10 参数 Datasheet PDF下载

EPM7256AEFC256-10图片预览
型号: EPM7256AEFC256-10
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 10ns, 256-Cell, CMOS, PBGA256, FINE LINE, BGA-256]
分类和应用: 时钟LTE输入元件可编程逻辑
文件页数/大小: 64 页 / 437 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 7000A Programmable Logic Device Data Sheet  
MAX 7000A devices use CMOS EEPROM cells to implement logic  
functions. The user-configurable MAX 7000A architecture accommodates  
a variety of independent combinatorial and sequential logic functions.  
The devices can be reprogrammed for quick and efficient iterations  
during design development and debug cycles, and can be programmed  
and erased up to 100 times.  
MAX 7000A devices contain from 32 to 512 macrocells that are combined  
into groups of 16 macrocells, called logic array blocks (LABs). Each  
macrocell has a programmable-AND/fixed-ORarray and a configurable  
register with independently programmable clock, clock enable, clear, and  
preset functions. To build complex logic functions, each macrocell can be  
supplemented with both shareable expander product terms and high-  
speed parallel expander product terms, providing up to 32 product terms  
per macrocell.  
MAX 7000A devices provide programmable speed/power optimization.  
Speed-critical portions of a design can run at high speed/full power,  
while the remaining portions run at reduced speed/low power. This  
speed/power optimization feature enables the designer to configure one  
or more macrocells to operate at 50% or lower power while adding only a  
nominal timing delay. MAX 7000A devices also provide an option that  
reduces the slew rate of the output buffers, minimizing noise transients  
when non-speed-critical signals are switching. The output drivers of all  
MAX 7000A devices can be set for 2.5 V or 3.3 V, and all input pins are  
2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used  
in mixed-voltage systems.  
MAX 7000A devices are supported by Altera development systems,  
which are integrated packages that offer schematic, text—including  
VHDL, Verilog HDL, and the Altera Hardware Description Language  
(AHDL)—and waveform design entry, compilation and logic synthesis,  
simulation and timing analysis, and device programming. The software  
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other  
interfaces for additional design entry and simulation support from other  
industry-standard PC- and UNIX-workstation-based EDA tools. The  
software runs on Windows-based PCs, as well as Sun SPARCstation, and  
HP 9000 Series 700/800 workstations.  
For more information on development tools, see the MAX+PLUS II  
Programmable Logic Development System & Software Data Sheet and the  
Quartus Programmable Logic Development System & Software Data Sheet.  
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Altera Corporation  
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