MAX 7000 Programmable Logic Device Family Data Sheet
Figures 16 through 22 show the package pin-out diagrams for MAX 7000
devices.
Figure 16. 44-Pin Package Pin-Out Diagram
Package outlines not drawn to scale.
1()
1()
Pin 34
Pin 1
6
5
4
3
2
1 44 43 42 41 40
7
39
38
37
36
35
34
33
32
31
30
29
I/O
(2) I/O/(TDI)
(2) I/O/(TDI)
I/O
8
I/O/(TDO) (2)
I/O
I/O
I/O
I/O/(TDO) (2)
9
I/O
I/O
I/O
10
11
12
13
14
15
16
17
I/O
GND
GND
I/O
I/O
VCC
I/O
EPM7032
EPM7032S
EPM7064
EPM7064S
VCC
I/O
I/O
I/O
I/O
I/O
(2) I/O/(TMS)
I/O
(2) I/O/(TMS)
EPM7032
I/O/(TCK) (2)
I/O
VCC
I/O
I/O/(TCK) (2)
I/O
VCC
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
18 19 20 21 22 23 24 25 26 27 28
Pin 12
Pin 23
44-Pin PLCC
44-Pin PQFP
1()
Pin 34
Pin 1
(2) I/O/(TDI)
I/O
I/O
I/O/(TDO) (2)
I/O
I/O
GND
I/O
EPM7032
I/O
VCC
EPM7032S
EPM7064
EPM7064S
I/O
I/O
I/O
(2) I/O/(TMS)
I/O/(TCK) (2)
I/O
VCC
I/O
I/O
GND
I/O
I/O
Pin 12
Pin 23
44-Pin TQFP
Notes:
(1) The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices.
(2) JTAG ports are available in MAX 7000S devices only.
Altera Corporation
59
ALTERA [ ALTERA CORPORATION ]
