MAX 7000 Programmable Logic Device Family Data Sheet
Table 38. EPM7256S Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-10
Unit
-7
-15
Min Max Min Max Min Max
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.3
0.3
3.4
3.9
1.1
2.6
2.6
0.8
0.5
1.0
5.5
4.0
4.5
9.0
4.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
8.0
6.0
7.0
10.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
C1 = 5 pF
1.1
1.6
2.4
2.0
3.0
3.0
4.0
4.0
2.0
SU
Register hold time
H
Register setup time of fast
input
FSU
t
Register hold time of fast
input
0.6
0.5
1.0
ns
FH
t
t
t
t
t
t
t
t
t
Register delay
1.1
1.1
2.9
2.6
2.8
2.7
2.7
3.0
10.0
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
11.0
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
13.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
COMB
IC
EN
GLOB
PRE
CLR
PIA
(7)
(8)
Low-power adder
LPA
52
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
