MAX 7000 Programmable Logic Device Family Data Sheet
Tables 37 and 38 show the EPM7256S AC operating conditions.
Table 37. EPM7256S External Timing Parameters
Symbol Parameter Conditions
Note (1)
Speed Grade
-10
Unit
-7
-15
Min Max Min Max Min Max
t
t
Input to non-registered output C1 = 35 pF
7.5
7.5
10.0
10.0
15.0
15.0
ns
ns
PD1
PD2
I/O input to non-registered
output
C1 = 35 pF
t
t
t
Global clock setup time
Global clock hold time
3.9
0.0
3.0
7.0
0.0
3.0
11.0
0.0
ns
ns
ns
SU
H
Global clock setup time of fast
input
3.0
FSU
t
Global clock hold time of fast
input
0.0
0.5
0.0
ns
FH
t
t
t
t
t
t
t
t
t
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
4.7
7.8
5.0
8.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
CO1
CH
3.0
3.0
0.8
1.9
4.0
4.0
2.0
3.0
5.0
5.0
4.0
4.0
CL
ASU
AH
C1 = 35 pF
10.0
15.0
ACO1
ACH
ACL
CPPW
3.0
3.0
3.0
4.0
4.0
4.0
6.0
6.0
6.0
Minimum pulse width for clear (2)
and preset
t
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
ns
ODH
t
f
Minimum global clock period
7.8
7.8
10.0
10.0
13.0
13.0
ns
CNT
CNT
Maximum internal global clock (4)
frequency
128.2
100.0
76.9
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock (4)
frequency
128.2
166.7
100.0
125.0
76.9
MHz
f
Maximum clock frequency
(5)
100.0
MHz
MAX
Altera Corporation
51
ALTERA [ ALTERA CORPORATION ]
