MAX 7000 Programmable Logic Device Family Data Sheet
Table 35. EPM7192S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-10
Min Max Min Max Min Max
Unit
-7
-15
t
t
t
t
t
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
1.8
3.0
4.0
ns
ns
ns
ns
ns
AH
C1 = 35 pF
7.8
10.0
15.0
ACO1
ACH
ACL
3.0
3.0
3.0
4.0
4.0
4.0
6.0
6.0
6.0
Minimum pulse width for clear (2)
CPPW
and preset
t
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
ns
ODH
t
f
Minimum global clock period
8.0
8.0
10.0
10.0
13.0
13.0
ns
CNT
CNT
Maximum internal global clock (4)
frequency
125.0
100.0
76.9
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock (4)
frequency
125.0
166.7
100.0
125.0
76.9
MHz
f
Maximum clock frequency
(5)
100.0
MHz
MAX
Table 36. EPM7192S Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-10
Unit
-7
-15
Min Max Min Max Min Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.3
0.3
3.2
4.2
1.2
3.1
3.1
0.9
0.5
1.0
5.5
4.0
4.5
9.0
4.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
7.0
6.0
7.0
10.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IO
FIN
Shared expander delay
Parallel expander delay
Logic array delay
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
C1 = 5 pF
1.1
2.0
4.0
SU
Altera Corporation
49
ALTERA [ ALTERA CORPORATION ]
