MAX 3000A Programmable Logic Device Family Data Sheet
Table 22. EPM3512A Internal Timing Parameters (Part 2 of 3)
Note (1)
Speed Grade
Symbol
Parameter
Conditions
Unit
-7
-10
Min
Max
Min
Max
tSEXP
Shared expander delay
Parallel expander delay
Logic array delay
2.7
0.4
2.2
1.0
0.0
1.0
3.5
0.5
2.8
1.3
0.0
1.5
ns
ns
ns
ns
ns
ns
tPEXP
tLAD
tLAC
tIOE
Logic control array delay
Internal output enable delay
tOD1
Output buffer and pad delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
tOD2
tOD3
tZX1
tZX2
tZX3
Output buffer and pad delay,
slow slew rate = off
VCCIO = 2.5 V
1.5
6.0
4.0
4.5
9.0
4.0
2.0
6.5
ns
ns
ns
ns
ns
Output buffer and pad delay,
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
Output buffer enable delay,
slow slew rate = off
VCCIO = 3.3 V
5.0
Output buffer enable delay,
slow slew rate = off
VCCIO = 2.5 V
5.5
Output buffer enable delay,
slow slew rate = on
VCCIO = 3.3 V
10.0
5.0
tXZ
Output buffer disable delay
Register setup time
Register hold time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU
2.1
0.6
1.6
1.4
3.0
0.8
1.6
1.4
tH
tFSU
tFH
Register setup time of fast input
Register hold time of fast input
Register delay
tRD
1.3
0.6
1.8
1.0
1.7
1.0
1.0
3.0
1.7
0.8
2.3
1.3
2.2
1.4
1.4
4.0
tCOMB
tIC
Combinatorial delay
Array clock delay
tEN
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
tGLOB
tPRE
tCLR
tPIA
(2)
Altera Corporation
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