MAX 3000A Programmable Logic Device Family Data Sheet
Table 18. EPM3128A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
–7
Unit
–5
–10
Min
Max Min
Max Min Max
tPIA
PIA delay
Low–power adder
(2)
(5)
1.4
4.0
2.0
4.0
2.6
5.0
ns
ns
tLPA
Table 19. EPM3256A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–7
–10
Min
Max
Min
Max
tPD1
Input to non–registered
output
C1 = 35 pF (2)
7.5
10
ns
ns
tPD2
I/O input to non–registered C1 = 35 pF (2)
7.5
4.8
10
output
tSU
tH
Global clock setup time
Global clock hold time
(2)
5.2
0.0
1.0
6.9
0.0
1.0
ns
ns
ns
(2)
tCO1
Global clock to output
delay
C1 = 35 pF
6.4
9.7
tCH
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
3.0
3.0
2.7
0.3
1.0
3.0
3.0
3.0
4.0
4.0
3.6
0.5
1.0
4.0
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
tCL
tASU
tAH
(2)
(2)
tACO1
tACH
tACL
tCPPW
Array clock to output delay C1 = 35 pF (2)
Array clock high time
7.3
Array clock low time
Minimum pulse width for
clear and preset
(3)
tCNT
Minimum global clock
period
(2)
7.9
7.9
10.5
10.5
ns
MHz
ns
fCNT
Maximum internal global
clock frequency
(2), (4)
(2)
126.6
126.6
95.2
95.2
tACNT
fACNT
Minimum array clock
period
Maximum internal array
clock frequency
(2), (4)
MHz
30
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
