MAX 3000A Programmable Logic Device Family Data Sheet
Table 20. EPM3256A Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–7
–10
Min
Max
Min
Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Shared expander delay
Parallel expander delay
Logic array delay
0.9
0.9
2.8
0.5
2.2
1.0
0.0
1.2
1.2
1.2
3.7
0.6
2.8
1.3
0.0
1.6
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tSEXP
tPEXP
tLAD
tLAC
tIOE
Logic control array delay
Internal output enable delay
tOD1
Output buffer and pad delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
tOD2
Output buffer and pad delay,
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
C1 = 35 pF
1.7
6.2
2.1
6.6
ns
ns
tOD3
Output buffer and pad delay,
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
tZX1
tZX2
tZX3
Output buffer enable delay, slow C1 = 35 pF
slew rate = off VCCIO = 3.3 V
4.0
4.5
9.0
5.0
5.5
ns
ns
ns
Output buffer enable delay, slow C1 = 35 pF
slew rate = off VCCIO = 2.5 V
Output buffer enable delay, slow C1 = 35 pF
slew rate = on
10.0
VCCIO = 2.5 V or 3.3 V
tXZ
Output buffer disable delay
Register setup time
Register hold time
Register delay
C1 = 5 pF
4.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU
2.1
0.9
2.9
1.2
tH
tRD
1.2
0.8
1.6
1.0
1.5
2.3
2.3
2.4
4.0
1.6
1.2
2.1
1.3
2.0
3.0
3.0
3.2
5.0
tCOMB
tIC
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
tEN
tGLOB
tPRE
tCLR
tPIA
tLPA
(2)
(5)
Low–power adder
Altera Corporation
31
ALTERA [ ALTERA CORPORATION ]
