Chapter 11: In-System Programmability Guidelines for MAX II Devices
IEEE Std. 1149.1 Signals
11–5
Further, because the
TCK
signal must drive all IEEE Std. 1149.1 devices in the chain in
parallel, the signal may have a high fan-out. Like any other high fan-out user-mode
clock, you must manage a clock tree to maintain signal integrity. Typical errors that
result from clock integrity problems are invalid ID messages, blank-check errors, or
verification errors.
Altera recommends pulling the
TCK
signal low through the internal weak pull-down
resistor or an external 1-kΩ resistor.
Fast
TCK
edges combined with board inductance can cause overshoot problems.
When this combination occurs, you must either reduce inductance on the trace or
reduce the switching rate by selecting a transistor-to-transistor logic (TTL) driver chip
with a slower slew rate. Altera does not recommend using resistor and capacitor (RC)
networks to slow down edge rates, because they can violate the device’s input
specifications. In most cases, using a driver chip prevents the edge rate from being too
slow. Altera recommends using driver chips that do not glitch upon power-up.
Programming via a Download Cable
You can program MAX II devices using a MasterBlaster
TM
, ByteBlasterMV
TM
,
ByteBlaster
TM
II, or USB Blaster download cable. Using a PC or UNIX workstation
with the Quartus II software programmer, Programmer Object File (.pof), JamTM
Files (.jam), or Jam Byte-Code Files (.jbc) can be downloaded to the MAX II devices
via the download cable.
If you are using the download cables and your JTAG chain contains three or more
devices, Altera recommends adding a buffer to the chain. You should select a buffer
with slow transitions to minimize noise, but be sure that the transition rates can still
meet
TCK
performance requirements of your chain.
If you must extend the download cable, you can attach a standard PC parallel or USB
port cable to the download cable. Do not extend the 10-pin header portion of the
download cable; extending this portion of the cable can cause noise and in-system
programming problems.
f
Different download cables will have different programming times. For more
information about the MasterBlaster, ByteBlasterMV, ByteBlaster II, or USB Blaster
download cable, refer to the
or
Disabling IEEE Std. 1149.1 Circuitry
By default, the JTAG circuitry in MAX II devices is always enabled because they have
dedicated JTAG pins and circuitry. The JTAG circuitry must be enabled during ISP
and boundary-scan testing, but disabled at all other times. If your design does not use
ISP or boundary-scan test (BST) circuitry, Altera recommends disabling the IEEE Std.
1149.1 circuitry.
To disable the JTAG circuitry, Altera recommends pulling
TMS
high and
TCK
low.
Pulling
TCK
low ensures that a rising edge does not occur on
TCK
during the power-
up sequence. You can pull
TCK
high, but you must first pull
TMS
high. Pulling
TMS
high first ensures that the rising edge or edges on
TCK
do not cause the JTAG state
machine to leave the test-logic-reset state.
ALTERA [ ALTERA CORPORATION ]
