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EPM240T100C5N 参数 Datasheet PDF下载

EPM240T100C5N图片预览
型号: EPM240T100C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 可编程逻辑器件输入元件PC
文件页数/大小: 295 页 / 3815 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 11: In-System Programmability Guidelines for MAX II Devices
ISP via Embedded Processors
11–9
Check the V
CC
Level of the Board During In-System Programming
Using an oscilloscope, monitor the V
CCINT
signal on your JTAG chain and set the
trigger to the minimum V
CC
level listed in the recommended operating conditions
table of the appropriate device family data sheet. If a trigger occurs during in-system
programming, the devices may need more current than is being supplied by the
existing power supply. Try replacing the existing power supply with one that
provides more current.
Power-Up Problems
Excessive voltage or current on I/O pins during power-up can cause one of the
devices in the JTAG chain to experience latch-up. Check if any of the devices are hot to
the touch; hot devices have probably experienced latch-up and may have been
damaged. In this situation, check all voltage sources to make sure that excessive
voltage or current is not being fed into the device. Then, replace the affected device
and try programming again.
Random Signals on JTAG Pins
During normal operation, each device’s TAP controller must be in the test-logic-reset
state. To force the device back into this state, try pulling the
TMS
signal high and
pulsing the
TCK
clock signal six times. If the device then powers-up successfully, you
must add a higher pull-down resistor on the
TCK
signal.
Software Issues
Failures during in-system programming may occasionally be related to the Quartus II
software. Software-related issues are documented in the Find Answers section under
the Support Center on the Altera website at
Search the database for
information relating to software issues that interfere with in-system programming.
ISP via Embedded Processors
This section provides guidelines for programming ISP-capable devices using the Jam
Standard Test and Programming Language (STAPL) and an embedded processor.
Processor and Memory Requirements
The Jam Byte-Code Player supports 8-bit and higher processors; the ASCII Jam Player
supports 16-bit and higher processors. The Jam Player uses memory in a predictable
manner, which simplifies in-field upgrades by confining updates to the Jam File. The
Jam Player memory uses both ROM and dynamic memory (RAM). ROM is used to
store the Jam Player binary and the Jam File; dynamic memory is used when the Jam
Player is called.
f
For information about how to estimate the maximum amount of RAM and ROM
required by the Jam Player, refer to the
chapter in the
MAX II Device Handbook.