9–6
Chapter 9: Using User Flash Memory in MAX II Devices
UFM Functional Description
Figure 9–3.
UFM Data Register
MAX II UFM Block
16
16
Data Register
DRDin
D0
LSB
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
MSB
DRDout
DRCLK
UFM Program/Erase Control Block
The UFM program/erase control block is used to generate all the control signals
necessary to program and erase the UFM block independently. This reduces the
number of LEs necessary to implement a UFM controller in the logic array. It also
guarantees correct timing of the control signals to the UFM. A rising edge on either
PROGRAM
or
ERASE
causes this control signal block to activate and begin sequencing
through the program or erase cycle. At this point, for a program instruction, whatever
data is in the data register will be written to the address pointed to by the address
register.
Only sector erase is supported by the UFM. Once an
ERASE
command is executed,
this control block will erase the sector whose address is stored in the address register.
When the
PROGRAM
or
ERASE
command first activates the program/erase control
block, the
BUSY
signal will be driven high to indicate an operation in progress in the
UFM. Once the program or erase algorithm is completed, the
BUSY
signal will be
forced low.
Oscillator
OSC_ENA,
one of the input signals in the UFM block, is used to enable the oscillator
signal to output through the
OSC
output port. You can use this
OSC
output port to
connect with the interface logic in the logic array. It can be routed through the logic
array and fed back as an input clock for the address register (ARCLK) and the data
register (DRCLK). The output frequency of the
OSC
port is one-fourth that of the
oscillator frequency. As a result, the frequency range of the
OSC
port is 3.3 to 5.5 MHz.
The maximum clock frequency accepted by
ARCLK
and
DRCLK
is 10 MHz and the
duty cycle accepted by the
DRCLK
and
ARCLK
input ports is approximately 45% to
50%.
When the
OSC_ENA
input signal is asserted, the oscillator is enabled and the output is
routed to the logic array through the
OSC
output. When the
OSC_ENA
is set low, the
OSC
output drives constant low. The routing delay from the
OSC
port of the UFM
block to
OSC
output pin depends on placement. You can analyze this delay using the
Quartus II timing analyzer.
ALTERA [ ALTERA CORPORATION ]
