Chapter 9: Using User Flash Memory in MAX II Devices
UFM Functional Description
9–3
UFM Functional Description
is the block diagram of the MAX II UFM block and the interface signals.
Figure 9–1.
UFM Block and Interface Signals
UFM Block
PROGRAM
ERASE
Program
Erase
Control
OSC
_4
:
RTP_BUSY
BUSY
OSC_ENA
OSC
9
ARCLK
UFM Sector 1
UFM Sector 0
Address
Register
16
ARSHFT
16
ARDin
DRDin
DRCLK
DRSHFT
Data Register
DRDout
summarizes the MAX II UFM block input and output interface signals.
Table 9–4.
UFM Interface Signals (Part 1 of 2)
Port Name
DRDin
Port Type
Input
Description
Serial input to the data register. It is used to enter a data word when
writing to the UFM. The data register is 16 bits wide and data is shifted
serially from the least significant bit (LSB) to the MSB with each
DRCLK.
This port is required for writing, but unused if the UFM is in
read-only mode.
Clock input that controls the data register. It is required and takes
control when data is shifted from
DRDin
to
DRDout
or loaded in
parallel from the flash memory. The maximum frequency for
DRCLK
is
10 MHz.
Signal that determines whether to shift the data register or load it on a
DRCLK
edge. A high value shifts the data from
DRDin
into the LSB of
the data register and from the MSB of the data register out to
DRDout.
A low value loads the value of the current address in the flash memory
to the data register.
Serial input to the address register. It is used to enter the address of a
memory location to read, program, or erase. The address register is
9 bits wide for the UFM size (8,192 bits).
DRCLK
Input
DRSHFT
Input
ARDin
Input
ALTERA [ ALTERA CORPORATION ]
