Chapter 9: Using User Flash Memory in MAX II Devices
9–3
UFM Functional Description
UFM Functional Description
Figure 9–1 is the block diagram of the MAX II UFM block and the interface signals.
Figure 9–1. UFM Block and Interface Signals
UFM Block
PROGRAM
ERASE
RTP_BUSY
BUSY
Program
Erase
Control
_
:
OSC_ENA
OSC
4
OSC
UFM Sector 1
UFM Sector 0
9
ARCLK
Address
Register
16
16
ARSHFT
ARDin
DRDin
Data Register
DRDout
DRCLK
DRSHFT
Table 9–4 summarizes the MAX II UFM block input and output interface signals.
Table 9–4. UFM Interface Signals (Part 1 of 2)
Port Name
Port Type
Description
DRDin
Input
Serial input to the data register. It is used to enter a data word when
writing to the UFM. The data register is 16 bits wide and data is shifted
serially from the least significant bit (LSB) to the MSB with each
DRCLK. This port is required for writing, but unused if the UFM is in
read-only mode.
DRCLK
Input
Input
Clock input that controls the data register. It is required and takes
control when data is shifted from DRDinto DRDoutor loaded in
parallel from the flash memory. The maximum frequency for DRCLKis
10 MHz.
DRSHFT
Signal that determines whether to shift the data register or load it on a
DRCLKedge. A high value shifts the data from DRDininto the LSB of
the data register and from the MSB of the data register out to DRDout.
A low value loads the value of the current address in the flash memory
to the data register.
ARDin
Input
Serial input to the address register. It is used to enter the address of a
memory location to read, program, or erase. The address register is
9 bits wide for the UFM size (8,192 bits).
© October 2008 Altera Corporation
MAX II Device Handbook
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