9–4
Chapter 9: Using User Flash Memory in MAX II Devices
UFM Functional Description
Table 9–4. UFM Interface Signals (Part 2 of 2)
Port Name
Port Type
Description
ARCLK
Input
Clock input that controls the address register. It is required when
shifting the address data from ARDininto the address register or
during the increment stage. The maximum frequency for ARCLKis 10
MHz.
ARSHFT
Input
Input
Signal that determines whether to shift the address register or
increment it on an ARCLKedge. A high value shifts the data from
ARDinserially into the address register. A low value increments the
current address by 1. The address register rolls over to 0 when the
address space is at the maximum.
PROGRAM
Signal that initiates a program sequence. On the rising edge, the data in
the data register is written to the address pointed to by the address
register. The BUSYsignal asserts until the program sequence is
completed.
ERASE
Input
Input
Signal that initiates an erase sequence. On a rising edge, the memory
sector indicated by the MSB of the address register will be erased. The
BUSYsignal asserts until the erase sequence is completed.
OSC_ENA
This signal turns on the internal oscillator in the UFM block, and is
optional but required when the OSCoutput is used. If OSC_ENAis
driven high, the internal oscillator is enabled and the OSCoutput will
toggle. If OSC_ENAis driven low, the internal oscillator is disabled and
the OSCoutput drives constant low.
DRDout
Output
Output
Serial output of the data register. Each time the DRCLKsignal is
applied, a new value is available. The DRDoutdata depends on the
DRSHFTsignal. When the DRSHFTsignal is high, DRDoutvalue is
the new value that is shifted into the MSB of the data register. If the
DRSHFTis low, DRDoutwould contain the MSB of the memory
location read into the data register.
BUSY
Signal that indicates when the memory is BUSYperforming a
PROGRAMor ERASE instruction. When it is high, the address and data
register should not be clocked. The new PROGRAMor ERASE
instruction will not be executed until the BUSYsignal is deasserted.
OSC
Output
Output
Output of the internal oscillator. It can be used to generate a clock to
control user logic with the UFM. It requires an OSCenable input to
produce an output.
RTP_BUSY
This output signal is optional and only needed if the real-time ISP
feature is used. The signal is asserted high during real-time ISP and
stays in the RUN_STATEfor 500 ms before initiating real-time ISP to
allow for the final read/erase/write operation. No read, write, erase, or
address and data shift operations are allowed to be issued once the
RTP_BUSYsignal goes high. The data and address registers do not
retain the contents of the last read or write operation for the UFM block
during real-time ISP.
f
To see the interaction between the UFM block and the logic array of MAX II devices,
refer to the MAX II Architecture chapter in the MAX II Device Handbook (Figure 2–16 for
EPM240 devices and Figure 2–17 for EPM570, EPM1270, and EPM2210 devices).
MAX II Device Handbook
© October 2008 Altera Corporation
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