Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5–23
JTAG Timing Specifications
shows the timing waveforms for the JTAG signals.
Figure 5–6.
MAX II JTAG Timing Waveforms
TMS
TDI
t
JCP
t
JCH
t
JCL
t
JPSU
t
JPH
TCK
t
JPZX
t
JPCO
t
JSSU
t
JSH
t
JPXZ
TDO
Signal
to
be
Captured
Signal
to
be
Driven
t
JSZX
t
JSCO
t
JSXZ
shows the JTAG Timing parameters and values for MAX II devices.
Table 5–31.
MAX II JTAG Timing Parameters (Part 1 of 2)
Symbol
t
JCP
Parameter
TCK
clock period for V
CCIO1
= 3.3 V
TCK
clock period for V
CCIO1
= 2.5 V
TCK
clock period for V
CCIO1
= 1.8 V
TCK
clock period for V
CCIO1
= 1.5 V
t
JCH
t
JCL
t
JPSU
t
JPH
t
JPCO
t
JPZX
t
JPXZ
t
JSSU
t
JSH
t
JSCO
TCK
clock high time
TCK
clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Min
55.5
62.5
100
143
20
20
8
10
—
—
—
8
10
—
Max
—
—
—
—
—
—
—
—
15
15
15
—
—
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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