Chapter 5: DC and Switching Characteristics
5–19
Timing Model and Specifications
Table 5–24 shows the external I/O timing parameters for EPM570 devices.
Table 5–24. EPM570 Global Clock External I/O Timing Parameters
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Symbol
Parameter
Condition Min Max Min Max Min
Max
Min Max Min Max Unit
tPD1
Worst case pin-to-pin
delay through 1 look-
up table (LUT)
10 pF
—
5.4
—
7.0
—
8.7
—
9.5
—
15.1
ns
tPD2
tSU
tH
Best case pin-to-pin
delay through 1 LUT
10 pF
—
—
1.2
0.0
2.0
166
3.7
—
—
1.5
0.0
2.0
216
4.8
—
—
1.9
0.0
2.0
266
5.9
—
—
2.6
0
5.7
—
—
4.5
0
7.7
—
ns
ns
ns
ns
ps
Global clock setup
time
Global clock hold
time
—
—
—
—
—
—
tCO
tCH
Global clock to
output delay
10 pF
—
4.5
—
5.8
—
7.1
—
2.0
253
6.1
—
2.0
335
7.6
—
Global clock high
time
tCL
Global clock low time
—
—
166
3.3
—
—
216
4.0
—
—
266
5.0
—
—
253
5.4
—
—
335
8.1
—
—
ps
ns
tCNT
Minimum global
clock period for
16-bit counter
fCNT
Maximum global
clock frequency for
16-bit counter
—
—
304.0
(1)
—
247.5
—
201.1
—
184.1
—
123.5 MHz
Note to Table 5–24:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock
input pin maximum frequency.
Table 5–25 shows the external I/O timing parameters for EPM1270 devices.
Table 5–25. EPM1270 Global Clock External I/O Timing Parameters (Part 1 of 2)
–3 Speed Grade
–4 Speed Grade –5 Speed Grade
Symbol
tPD1
Parameter
Condition
Min
Max
Min
Max
Min
Max
Unit
Worst case pin-to-pin
delay through 1 look-up
table (LUT)
10 pF
—
6.2
—
8.1
—
10.0
ns
tPD2
Best case pin-to-pin
delay through 1 LUT
10 pF
—
3.7
—
4.8
—
5.9
ns
tSU
tH
Global clock setup time
Global clock hold time
—
—
1.2
0.0
2.0
—
—
1.5
0.0
2.0
—
—
1.9
0.0
2.0
—
—
ns
ns
ns
tCO
Global clock to output
delay
10 pF
4.6
5.9
7.3
tCH
tCL
Global clock high time
Global clock low time
—
—
166
166
—
—
216
216
—
—
266
266
—
—
ps
ps
© Novermber 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
