5–18
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–23 shows the external I/O timing parameters for EPM240 devices.
Table 5–23. EPM240 Global Clock External I/O Timing Parameters
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Symbol
Parameter
Condition Min Max Min Max Min Max Min Max Min Max
Unit
tPD1
Worst case
pin-to-pin
10 pF
—
4.7
—
6.1
—
7.5
—
7.9
—
12.0
ns
delay through
1 look-up
table (LUT)
tPD2
Best case pin-
to-pin delay
through
10 pF
—
3.7
—
4.8
—
5.9
—
5.8
—
7.8
ns
1 LUT
tSU
tH
Global clock
setup time
—
—
1.7
0.0
2.0
—
—
2.2
0.0
2.0
—
—
2.7
0.0
2.0
—
—
2.8
0
—
—
4.7
0
—
—
ns
ns
ns
Global clock
hold time
tCO
Global clock
to output
delay
10 pF
4.3
5.6
6.9
2.0
7.7
2.0
10.5
tCH
tCL
Global clock
high time
—
—
—
166
166
3.3
—
—
—
216
216
4.0
—
—
—
266
266
5.0
—
—
—
253
253
5.4
—
—
—
335
335
8.1
—
—
—
ps
ps
ns
Global clock
low time
tCNT
Minimum
global clock
period for
16-bit counter
fCNT
Maximum
—
—
304.0
(1)
—
247.5
—
201.1
—
184.1
—
123.5 MHz
global clock
frequency for
16-bit counter
Note to Table 5–23:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
MAX II Device Handbook
© Novermber 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
