Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5–21
External Timing I/O Delay Adders
The I/O delay timing parameters for I/O standard input and output adders, and
input delays are specified by speed grade independent of device density.
through
show the adder delays associated with I/O pins for all
packages. The delay numbers for –3, –4, and –5 speed grades shown in
through
are based on an EPM1270 device target, while –6 and –7 speed
grade values are based on an EPM570Z device target. If an I/O standard other than
3.3-V LVTTL is selected, add the input delay adder to the external t
SU
timing
parameters shown in
through
If an I/O standard other than
3.3-V LVTTL with 16 mA drive strength and fast slew rate is selected, add the output
delay adder to the external t
CO
and t
PD
shown in
through
Table 5–27.
External Timing Input Delay Adders
–3 Speed
Grade
Standard
3.3-V LVTTL
Without Schmitt
Trigger
With
Schmitt Trigger
3.3-V
LVCMOS
Without Schmitt
Trigger
With
Schmitt Trigger
2.5-V LVTTL
Without Schmitt
Trigger
With Schmitt
Trigger
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI
Without Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
—
—
—
—
—
23
339
291
681
0
—
—
—
—
—
30
441
378
885
0
—
—
—
—
—
37
543
466
1,090
0
—
—
—
—
—
42
429
378
681
0
—
—
—
—
—
43
476
373
622
0
ps
ps
ps
ps
ps
—
—
0
334
—
—
0
434
—
—
0
535
—
—
0
387
—
—
0
434
ps
ps
Min
—
—
Max
0
334
–4 Speed
Grade
Min
—
—
Max
0
434
–5 Speed
Grade
Min
—
—
Max
0
535
–6 Speed
Grade
Min
—
—
Max
0
387
–7 Speed
Grade
Min
—
—
Max
0
434
Unit
ps
ps
Table 5–28.
MAX II IOE Programmable Delays
–3 Speed
Grade
Parameter
Input Delay from Pin to Internal
Cells = 1
Input Delay from Pin to Internal
Cells = 0
Min
—
—
Max
1,225
89
–4 Speed
Grade
Min
—
—
Max
1,592
115
–5 Speed
Grade
Min
—
—
Max
1,960
142
–6 Speed
Grade
Min
—
—
Max
1,858
569
–7 Speed
Grade
Min
—
—
Max
2,171
609
Unit
ps
ps
ALTERA [ ALTERA CORPORATION ]
