Chapter 5: DC and Switching Characteristics
5–17
Timing Model and Specifications
Figure 5–5. UFM Erase Waveform
ARShft
tASU
ARClk
9 Address Bits
tACLK
tAH
tADH
ARDin
tADS
DRShft
DRClk
DRDin
DRDout
OSC_ENA
tOSCS
tEB
tOSCH
Program
Erase
tBE
Busy
tEPMX
Table 5–22. Routing Delay Internal Timing Microparameters
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Routing
Min
Max
Min
Max
Min
Max
687
521
529
Min
Max
(1)
Min
Max
(1)
Unit
ps
tC4
tR4
—
—
—
429
326
330
—
—
—
556
423
429
—
—
—
—
—
—
—
—
—
(1)
(1)
ps
tLOCAL
(1)
(1)
ps
Note to Table 5–22:
(1) The numbers will only be available in a later revision.
External Timing Parameters
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in Table 5–27 through Table 5–28.
f
For more information about each external timing parameters symbol, refer to the
Understanding Timing in MAX II Devices chapter in the MAX II Device Handbook.
© Novermber 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
