FLEX 6000 Programmable Logic Device Family Data Sheet
Open-drain output pins on 5.0-V or 3.3-V FLEX 6000 devices (with a pull-
up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that
require a VIH of 3.5 V. When the open-drain pin is active, it will drive low.
When the pin is inactive, the trace will be pulled up to 5.0 V by the resistor.
The open-drain pin will only drive low or tri-state; it will never drive high.
The rise time is dependent on the value of the pull-up resistor and load
impedance. The IOL current specification should be considered when
selecting a pull-up resistor.
Output pins on 5.0-V FLEX 6000 devices with VCCIO = 3.3 V or 5.0 V (with
a pull-up resistor to the 5.0-V supply) can also drive 5.0-V CMOS input
pins. In this case, the pull-up transistor will turn off when the pin voltage
exceeds 3.3 V. Therefore, the pin does not have to be open-drain.
Power Sequencing & Hot-Socketing
Because FLEX 6000 family devices can be used in a mixed-voltage
environment, they have been designed specifically to tolerate any possible
power-up sequence. The VCCIO and VCCINT power planes can be powered
in any order.
Signals can be driven into 3.3-V FLEX 6000 devices before and during
power up without damaging the device. Additionally, FLEX 6000 devices
do not drive out during power up. Once operating conditions are reached,
FLEX 6000 devices operate as specified by the user.
All FLEX 6000 devices provide JTAG BST circuitry that comply with the
IEEE Std. 1149.1-1990 specification. Table 8 shows JTAG instructions for
FLEX 6000 devices. JTAG BST can be performed before or after
configuration, but not during configuration (except when you disable
JTAG support in user mode).
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
1
See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan
Testing in Altera Devices) for more information on JTAG BST
circuitry.
Table 8. FLEX 6000 JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test result at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through the selected device to adjacent devices during
normal device operation.
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