FLEX 6000 Programmable Logic Device Family Data Sheet
The instruction register length for FLEX 6000 devices is three bits. Table 9
shows the boundary-scan register length for FLEX 6000 devices.
Table 9. FLEX 6000 Device Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EPF6010A
EPF6016
522
621
522
666
EPF6016A
EPF6024A
FLEX 6000 devices include a weak pull-up on JTAG pins.
See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices) for more information.
f
Figure 16 shows the timing requirements for the JTAG signals.
Figure 16. JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to Be
Driven
Table 10 shows the JTAG timing parameters and values for FLEX 6000
devices.
Altera Corporation
29
ALTERA [ ALTERA CORPORATION ]
