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EPF6024ABC256-3 参数 Datasheet PDF下载

EPF6024ABC256-3图片预览
型号: EPF6024ABC256-3
PDF下载: 下载PDF文件 查看货源
内容描述: [Loadable PLD, CMOS, PBGA256, BGA-256]
分类和应用: 时钟LTE输入元件可编程逻辑
文件页数/大小: 52 页 / 374 K
品牌: ALTERA [ ALTERA CORPORATION ]
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FLEX 6000 Programmable Logic Device Family Data Sheet  
Each IOE drives a row or column interconnect when used as an input or  
bidirectional pin. A row IOE can drive up to six row lines; a column IOE  
can drive up to two column lines. The input path from the I/O pad to the  
FastTrack Interconnect has a programmable delay element that can be  
used to guarantee a zero hold time. Depending on the placement of the  
IOE relative to what it is driving, the designer may choose to turn on the  
programmable delay to ensure a zero hold time. Figure 13 shows how an  
IOE connects to a row interconnect, and Figure 14 shows how an IOE  
connects to a column interconnect.  
Figure 13. IOE Connection to Row Interconnect  
Row Interconnect  
Any LE can drive  
a pin through the  
row and local  
interconnect.  
Up to 10 IOEs are on either  
side of a row. Each IOE can  
drive up to six row  
IOE  
LAB  
channels, and each IOE data  
and OE signal is driven by  
the local interconnect.  
IOE  
FastFLEX I/O: An LE can drive a pin through the  
local interconnect for faster clock-to-output times.  
24  
Altera Corporation  
 
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