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EPF6024ABC256-3 参数 Datasheet PDF下载

EPF6024ABC256-3图片预览
型号: EPF6024ABC256-3
PDF下载: 下载PDF文件 查看货源
内容描述: [Loadable PLD, CMOS, PBGA256, BGA-256]
分类和应用: 时钟LTE输入元件可编程逻辑
文件页数/大小: 52 页 / 374 K
品牌: ALTERA [ ALTERA CORPORATION ]
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FLEX 6000 Programmable Logic Device Family Data Sheet  
Figure 10. LAB Connections to Row & Column Interconnects  
Each LE FastTrack Interconnect  
output can drive six row channels.  
Each local channel  
driven by an LE can  
drive two column  
channels.  
Each LE output signal driving  
the FastTrack Interconnect can  
drive two column channels.  
At each intersection,  
four row channels can  
drive column channels.  
Row  
Interconnect  
Each local channel  
driven by an LE can  
drive four row channels.  
Row interconnect  
drives the local  
interconnect.  
LE  
From Adjacent  
Local Interconnect  
LE  
Local Interconnect  
Column Interconnect  
Any column channel can  
drive six row channels.  
An LE can be driven by any signal  
from two local interconnect areas.  
For improved routability, the row interconnect consists of full-length and  
half-length channels. The full-length channels connect to all LABs in a  
row; the half-length channels connect to the LABs in half of the row. In  
addition to providing a predictable, row-wide interconnect, this  
architecture provides increased routing resources. Two neighboring LABs  
can be connected using a half-length channel, which saves the other half  
of the channel for the other half of the row. One-third of the row channels  
are half-length channels.  
20  
Altera Corporation  
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