FLEX 6000 Programmable Logic Device Family Data Sheet
Table 20. IOE Timing Microparameters
Note (1)
Parameter
Symbol
Conditions
tOD1
tOD2
tOD3
tXZ
Output buffer and pad delay, slow slew rate = off, VCCIO = VCCINT
Output buffer and pad delay, slow slew rate = off, VCCIO = low voltage
Output buffer and pad delay, slow slew rate = on
Output buffer disable delay
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
C1 = 5 pF
tZX1
Output buffer enable delay, slow slew rate = off, VCCIO = VCCINT
Output buffer enable delay, slow slew rate = off, VCCIO = low voltage
IOE output buffer enable delay, slow slew rate = on
Output enable control delay
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
tZX2
tZX3
tIOE
tIN
Input pad and buffer to FastTrack Interconnect delay
tIN_DELAY
Input pad and buffer to FastTrack Interconnect delay with additional delay
turned on
Table 21. Interconnect Timing Microparameters
Note (1)
Symbol Parameter
Conditions
tLOCAL
LAB local interconnect delay
tROW
Row interconnect routing delay
Column interconnect routing delay
Dedicated input to LE data delay
Dedicated input to LE control delay
(5)
(5)
(5)
tCOL
tDIN_D
tDIN_C
tLEGLOBAL
tLABCARRY
LE output to LE control via internally-generated global signal delay
(5)
Routing delay for the carry-out of an LE driving the carry-in signal of a
different LE in a different LAB
tLABCASC
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Table 22. External Reference Timing Parameters
Symbol Parameter
Conditions
t1
tDRR
Register-to-register test pattern
(6)
(7)
Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local
interconnects
Altera Corporation
39
ALTERA [ ALTERA CORPORATION ]
