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EPCS4SI8N 参数 Datasheet PDF下载

EPCS4SI8N图片预览
型号: EPCS4SI8N
PDF下载: 下载PDF文件 查看货源
内容描述: 串行配置器件 [Serial Configuration Devices]
分类和应用: 存储内存集成电路光电二极管过程控制系统PCSLTE可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 38 页 / 686 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
Pin Information
3–33
Pin Information
As shown in
and
the serial configuration device is an 8-pin or
16-pin device. The control pins on the serial configuration device are: serial data
output (DATA), active serial data input (ASDI), serial clock (DCLK), and chip select
(nCS).
lists the serial configuration device's pin descriptions.
shows the Altera serial configuration device 8-pin SOIC package and its
pin-out diagram.
Figure 3–21.
Altera Serial Configuration Device 8-Pin SOIC Package Pin-Out Diagram
EPCS1, EPCS4,
or EPCS16
nCS
DATA
V
CC
GND
1
2
3
4
8
7
6
5
V
CC
V
CC
DCLK
ASDI
shows the Altera serial configuration device 16-pin SOIC package and its
pin-out diagram.
Figure 3–22.
Altera Serial Configuration Device 16-Pin SOIC Package Pin-Out Diagram
EPCS16,
EPCS64,
or EPCS128
V
CC
V
CC
N.C.
N.C.
N.C.
N.C.
nCS
DATA
1
2
3
(1)
4
(1)
5
(1)
6
(1)
7
8
16
15
14
(1)
13
(1)
12
(1)
11
(1)
10
9
DCLK
ASDI
N.C.
N.C.
N.C.
N.C.
GND
V
CC
Note to
(1) These pins can be left floating or connected to V
CC
or GND, whichever is more convenient on the board.
Table 3–23.
Serial Configuration Device Pin Description (Part 1 of 2)
Pin Number
in 8-Pin
SOIC
Package
2
Pin Number
in 16-Pin
SOIC
Package
8
Pin
Name
DATA
Pin Type
Output
Description
The
DATA
output signal transfers data serially out of the serial
configuration device to the FPGA during read/configuration operation.
During read/configuration operations, the serial configuration device
is enabled by pulling
nCS
low. The
DATA
signal transitions on the
falling edge of
DCLK.
The AS data input signal is used to transfer data serially into the serial
configuration device. It receives the data that should be programmed
into the serial configuration device. Data is latched on the rising edge
of
DCLK.
ASDI
5
15
Input