Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
After the first FPGA completes configuration, its
nCEO
pin asserts to
activate the second FPGA’s
nCE
pin, which prompts the second device to
start capturing configuration data. In this setup, the FPGAs
CONF_DONE
pins are tied together, and hence all devices initialize and enter user mode
simultaneously. If the enhanced configuration device or one of the FPGAs
detects an error, configuration stops (and simultaneously restarts) for the
whole chain because the
nSTATUS
pins are tied together.
1
While Altera FPGAs can be cascaded in a configuration chain,
the enhanced configuration devices cannot be cascaded to
configure larger devices/chains.
f
For configuration schematics and more information on multi-device FPP
configuration, refer to the appropriate FPGA family chapter in the
Configuration Handbook.
Passive Serial Configuration
Stratix series, Cyclone series, APEX II, APEX 20KC, APEX 20KE,
APEX 20K, and FLEX 10K devices can be configured using enhanced
configuration devices in the PS mode. This mode is similar to the FPP
mode, with the exception that only one bit of data (DATA[0]) is
transmitted to the FPGA per
DCLK
cycle. The remaining
DATA[7..1]
output pins are unused in this mode and drive low.
The configuration schematic for PS configuration of a single FPGA or
single serial chain is identical to the FPP schematic (with the exception
that only
DATA[0]
output from the enhanced configuration device
connects to the FPGA
DATA0
input pin; remaining
DATA[7..1]
pins are
left floating).
f
For configuration schematics and more information on multi-device PS
configuration, refer to the appropriate FPGA family chapter in the
Configuration Handbook.
Concurrent Configuration
The enhanced configuration device supports concurrent configuration of
multiple FPGAs (or FPGA chains) in PS mode. Concurrent configuration
is when the enhanced configuration device simultaneously outputs n bits
of configuration data on the
DATA[n-1..0]
pins (n = 1, 2, 4, or 8), and
each
DATA[]
line serially configures a different FPGA (chain). The
number of concurrent serial chains is user-defined via the Quartus II
software and can be any number between 1 and 8. For example, three
concurrent chains you can select the 4-bit PS mode, and connect the least
Altera Corporation
August 2005
2–9
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
