Functional Description
Figure 2–2. FPP Configuration
V
CC
(1)
V
CC
(1)
Stratix Series
or
APEX II Device
n
(6)
MSEL
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
(1)
V
CC
N.C.
nCEO
nCE
Enhanced Configuration
Device
(3)
(3)
WE#C
WE#F
RP#C
RP#F
DCLK
A[20..0]
DATA[7..0]
OE
(3)
RY/BY#
nCS
(3)
CE#
nINIT_CONF
(2)
OE#
DQ[15..0]
WP#
BYTE#
(5)
TM1
V
CC
(1)
VCCW
PORSEL
PGM[2..0]
TMO
EXCLK
(4)
(4)
(4)
N.C.
N.C.
N.C.
N.C.
N.C.
GND
GND
C-A0
(5)
C-A1
(5)
C-A15
(5)
C-A16
(5)
A0-F
A1-F
A15-F
A16-F
Notes to
(1)
(2)
The V
CC
should be connected to the same supply voltage as the configuration device.
The
nINIT_CONF
pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the
nINIT_CONF/nCONFIG
line. The
nINIT_CONF
pin does not need to be connected if its functionality is not used. If
nINIT_CONF
is not used,
nCONFIG
must be pulled to V
CC
either directly or through a resistor.
The enhanced configuration devices’
OE
and
nCS
pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus
®
II software. To turn off the internal pull-up resistors, check the
Disable nCS and
OE pull-ups on configuration device
option when generating programming files.
For
PORSEL, PGM[],
and
EXCLK
pin connections, refer to
In the 100-pin PQFP package, you must externally connect the following pins:
C-A0
to
F-A0, C-A1
to
F-A1, C-A15
to
F-A15, C-A16
to
F-A16,
and
BYTE#
to V
CC
. Additionally, you must make the following pin connections in both
100-pin PQFP and 88-pin Ultra FineLine BGA packages:
C-RP#
to
F-RP#, C-WE#
to
F-WE#, TM1
to V
CC
,
TM0
to
GND, and
WP#
to V
CC
.
Connect the FPGA
MSEL[]
input pins to select the FPP configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
(3)
(4)
(5)
(6)
Multiple FPGAs can be configured using a single enhanced configuration
device in FPP mode. In this mode, multiple Stratix series and/or APEX II
FPGAs are cascaded together in a daisy chain.
2–8
Configuration Handbook, Volume 2
Altera Corporation
August 2005
ALTERA [ ALTERA CORPORATION ]
