Functional Description
Figure 2–2. FPP Configuration
Enhanced Configuration
Device
V
CC
V
CC
(1)
(1)
Stratix Series
or
APEX II Device
WE#C
WE#F
(3)
(3)
RP#C
RP#F
DCLK
n
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
(6)
MSEL
A[20..0]
RY/BY#
CE#
N.C.
N.C.
N.C.
N.C.
N.C.
DATA[7..0]
(3)
OE
(3)
nCS
nINIT_CONF (2)
OE#
V
CC
(1)
DQ[15..0]
nCE
N.C.
nCEO
V
(1)
WP#
CC
BYTE# (5)
TM1
VCCW
GND
(4)
PORSEL
(4)
PGM[2..0]
(4)
TMO
EXCLK
GND
C-A0 (5)
C-A1 (5)
C-A15 (5)
C-A16 (5)
A0-F
A1-F
A15-F
A16-F
Notes to Figure 2–2:
(1) The VCC should be connected to the same supply voltage as the configuration device.
(2) The nINIT_CONFpin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIGline. The
nINIT_CONFpin does not need to be connected if its functionality is not used. If nINIT_CONFis not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ OEand nCSpins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus® II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
(4) For PORSEL, PGM[], and EXCLKpin connections, refer to Table 2–9.
(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0to F-A0, C-A1to F-A1, C-A15
to F-A15, C-A16to F-A16, and BYTE#to VCC. Additionally, you must make the following pin connections in both
100-pin PQFP and 88-pin Ultra FineLine BGA packages: C-RP#to F-RP#, C-WE#to F-WE#, TM1to VCC, TM0to
GND, and WP#to VCC
.
(6) Connect the FPGA MSEL[]input pins to select the FPP configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
Multiple FPGAs can be configured using a single enhanced configuration
device in FPP mode. In this mode, multiple Stratix series and/or APEX II
FPGAs are cascaded together in a daisy chain.
2–8
Altera Corporation
August 2005
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
