Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
Fast Passive Parallel Configuration
Stratix series and APEX II devices can be configured using the enhanced
configuration device in FPP mode. In this mode, the enhanced
configuration device sends a byte of data on the DATA[7..0]pins,
which connect to the DATA[7..0]input pins of the FPGA, per DCLK
cycle. Stratix series and APEX II FPGAs receive byte-wide configuration
data per DCLKcycle. Figure 2–2 shows the enhanced configuration device
in FPP configuration mode. In this figure, the external flash interface is
not used and hence most flash pins are left unconnected (with the few
noted exceptions). For specific details on configuration interface
connections including pull-up resistor values, supply voltages, and MSEL
pin settings, refer to the appropriate FPGA family chapter in the
Configuration Handbook.
Altera Corporation
August 2005
2–7
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
