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EP3C5E144C8N 参数 Datasheet PDF下载

EP3C5E144C8N图片预览
型号: EP3C5E144C8N
PDF下载: 下载PDF文件 查看货源
内容描述: 能够禁用外部JTAG端口 [Ability to disable external JTAG port]
分类和应用: 现场可编程门阵列可编程逻辑PC时钟
文件页数/大小: 348 页 / 6766 K
品牌: ALTERA [ ALTERA CORPORATION ]
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8–8  
Chapter 8: External Memory Interfaces in the Cyclone III Device Family  
Cyclone III Device Family Memory Interfaces Pin Support  
f
1
For more information about device package outline, refer to the Package and Thermal  
Resistance page.  
DQSpins are listed in the Cyclone III and Cyclone III LS pin tables as DQSXY, in which  
indicates the DQSgrouping number and indicates whether the group is located on  
the top ( ), bottom ( ), left ( ) or right ( ) side of the device. Similarly, the  
corresponding DQpins are marked as DQXY, in which the denotes the DQ grouping  
number and denotes whether the group is located on the top ( ), bottom ( ), left (  
or right ( ) side of the device. For example, DQS2Tindicates a DQSpin belonging to  
group , located on the top side of the device. Similarly, the DQpins belonging to that  
group is shown as DQ2T  
X
Y
T
B
L
R
X
Y
T
B
L)  
R
2
.
Each DQgroup is associated with its corresponding DQSpins, as defined in the Cyclone  
III and Cyclone III LS pin tables; for example:  
For DDR2 or DDR SDRAM, ×8 DQgroup DQ3B[7:0]pins are associated with  
the DQS3Bpin (same 3B group index)  
For QDR II SRAM, ×9 Q read-data group DQ3L[8..0]pins are associated with  
DQS2L/CQ3Land DQS3L/CQ3L#pins (same 3L group index)  
The Quartus® II software issues an error message if a DQgroup is not placed properly  
with its associated DQS  
.
Figure 8–2 shows the location and numbering of the DQS, DQ, or CQ# pins in the  
Cyclone III device family I/O banks.  
1
For maximum timing performance, Altera recommends that the data groups for  
external memory interfaces must always be within the same side of a device.  
Cyclone III Device Handbook  
Volume 1  
December 2011 Altera Corporation  
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