6–20
Chapter 6: I/O Features in the Cyclone III Device Family
I/O Banks
f
For more information about the Cyclone III device family I/O interface with 3.3-, 3.0-,
or 2.5-V
LVTTL/LVCMOS
systems, refer to
High-Speed Differential Interfaces
The Cyclone III device family can send and receive data through
LVDS
signals. For
the
LVDS
transmitter and receiver, the input and output pins of the Cyclone III device
family support serialization and deserialization through internal logic.
The
BLVDS
extends the benefits of
LVDS
to multipoint applications such as in
bidirectional backplanes. The loading effect and the need to terminate the bus at both
ends for multipoint applications require
BLVDS
to drive out a higher current than
LVDS
to produce a comparable voltage swing. All the I/O banks of the Cyclone III
device family support
BLVDS
for user I/O pins.
The reduced swing differential signaling (RSDS) and
mini-LVDS
standards are
derivatives of the
LVDS
standard. The
RSDS
and
mini-LVDS
I/O standards are
similar in electrical characteristics to
LVDS,
but have a smaller voltage swing and
therefore provide increased power benefits and reduced electromagnetic interference
(EMI).
The point-to-point differential signaling (PPDS) standard is the next generation of the
RSDS
standard introduced by National Semiconductor Corporation. The Cyclone III
device family meets the National Semiconductor Corporation PPDS Interface
Specification and supports the
PPDS
standard for outputs only. All the I/O banks of
the Cyclone III device family support the
PPDS
standard for output pins only.
You can use I/O pins and internal logic to implement the
LVDS
I/O receiver and
transmitter in the Cyclone III device family. Cyclone III and Cyclone III LS devices do
not contain dedicated serialization or deserialization circuitry. Therefore, shift
registers, internal PLLs, and IOEs are used to perform serial-to-parallel conversions
on incoming data and parallel-to-serial conversion on outgoing data.
The
LVDS
standard does not require an input reference voltage, but it does require a
100- termination resistor between the two signals at the input buffer. An external
resistor network is required on the transmitter side for top and bottom I/O banks.
f
For more information about the Cyclone III device family high-speed differential
interface support, refer to the
chapter.
External Memory Interfacing
The Cyclone III device family supports I/O standards required to interface with a
broad range of external memory interfaces, such as DDR SDRAM, DDR2 SDRAM,
and QDRII SRAM.
f
For more information about the Cyclone III device family external memory interface
support, refer to the
chapter.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
