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EP3C16Q144C6N 参数 Datasheet PDF下载

EP3C16Q144C6N图片预览
型号: EP3C16Q144C6N
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7308 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 6: I/O Features in the Cyclone III Device Family  
6–19  
I/O Banks  
Table 6–6. Number of VREF Pins Per I/O Banks for Cyclone III and Cyclone III LS Devices (Part 2 of 2)  
I/O Banks  
Family  
Device  
Package  
Pin Count  
1
3
3
3
3
3
3
3
3
3
3
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
3
3
3
3
3
3
3
3
3
3
5
3
3
3
3
3
3
3
3
3
3
6
3
3
3
3
3
3
3
3
3
3
7
3
3
3
3
3
3
3
3
3
3
8
3
3
3
3
3
3
3
3
3
3
UBGA  
FBGA  
FBGA  
UBGA  
FBGA  
FBGA  
FBGA  
FBGA  
FBGA  
FBGA  
278  
278  
413  
278  
278  
413  
210  
413  
210  
413  
EP3CLS70  
EP3CLS100  
EP3CLS150  
EP3CLS200  
Each I/O bank of the Cyclone III device family has its own VCCIOpins. Each I/O bank  
can support only one VCCIO setting from among 1.2, 1.5, 1.8, 3.0, or 3.3 V. Any number  
of supported single-ended or differential standards can be simultaneously supported  
in a single I/O bank, as long as they use the same VCCIO levels for input and output  
pins.  
When designing LVTTL/LVCMOS inputs with Cyclone III and Cyclone III LS  
devices, refer to the following guidelines:  
All pins accept input voltage (VI) up to a maximum limit (3.6 V), as stated in the  
recommended operating conditions are provided in the Cyclone III Device Data  
Sheet and Cyclone III LS Device Data Sheet chapters.  
Whenever the input level is higher than the bank VCCIO, expect higher leakage  
current.  
The LVTTL/LVCMOS I/O standard input pins can only meet the VIH and VIL  
levels according to bank voltage level.  
Voltage-referenced standards are supported in an I/O bank using any number of  
single-ended or differential standards, as long as they use the same VREF and VCCIO  
values. For example, if you choose to implement both SSTL-2 and SSTL-18 in your  
Cyclone III and Cyclone III LS devices, I/O pins using these standards—because they  
require different VREF values—must be in different banks from each other. However,  
the same I/O bank can support SSTL-2 and 2.5-V LVCMOS with the VCCIO set to  
2.5 V and the VREF set to 1.25 V.  
1
1
When using Cyclone III and Cyclone III LS devices as a receiver in 3.3-, 3.0-, or 2.5-V  
LVTTL/LVCMOS systems, you are responsible for managing overshoot or  
undershoot to stay in the absolute maximum ratings and the recommended operating  
conditions, provided in the Cyclone III Device Data Sheet and Cyclone III LS Device Data  
Sheet chapters.  
The PCI clamping diode is enabled by default in the Quartus II software for input  
signals with bank VCCIO at 2.5, 3.0, or 3.3 V.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1