5–34
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Document Revision History
Document Revision History
lists the revision history for this document.
Table 5–11. Document Revision History (Part 1 of 2)
Date
July 2012
Version
4.1
Updated
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Changes
Minor edits to Equation 5–1 and Equation 5–2.
Updated Table 5–5.
Updated Figure 5–6, Figure 5–13, Figure 5–19, and Figure 5–24.
Updated “Clock Control Block” on page 5–4, “Manual Override” on page 5–20, “PLL
Cascading” on page 5–24, and “Dynamic Phase Shifting” on page 5–31.
Minor text edits.
November 2011
4.0
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December 2009
July 2009
3.2
3.1
Minor changes to the text.
Made minor correction to the part number.
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Updated to include Cyclone III LS information.
Updated chapter part number.
Updated “Clock Networks” on page 5–1.
Updated Table 5–1 on page 5–2, Table 5–3 on page 5–9.
Updated “PLLs in the Cyclone III Device Family” on page 5–9.
Updated “PLL Reconfiguration Hardware Implementation” on page 5–25.
Updated “Spread-Spectrum Clocking” on page 5–32.
Updated the “Dynamic Phase Shifting” and “Introduction” sections.
Updated Figure 5–2, Figure 5–8, and Figure 5–24.
Updated chapter to new template.
Updated Figure 5–2 and added (Note 3).
Updated “clkena Signals” section.
Updated Figure 5–8 and added (Note 3).
Updated “PLL Control Signals” section.
Updated “PLL Cascading” section.
Updated “Cyclone III PLL Hardware Overview” section.
Updated Table 5–6, Table 5–3, Table 5–7.
Updated Figure 5–14.
Updated “PLL Cascading” section.
Updated “Clock Multiplication and Division” section.
Updated Step 6–32 in “PLL Reconfiguration Hardware Implementation” section.
Updated “Spread-Spectrum Clocking” section.
Updated Figure 5–29.
Updated “VCCD and GND” section.
Added “Power Consumption” section.
Updated “Board Layout” section and removed Figure 5-30.
June 2009
3.0
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October 2008
2.1
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May 2008
2.0
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September 2007
1.2
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Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
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