5–10
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Cyclone III Device Family PLL Hardware Overview
Cyclone III Device Family PLL Hardware Overview
This section gives a hardware overview of the Cyclone III device family PLL.
shows a simplified block diagram of the major components of the PLL of
the Cyclone III device family.
Figure 5–6. Cyclone III Device Family PLL Block Diagram
LOCK
circuit
÷C0
Clock inputs
from pins
4
inclk0
Clock
Switchover
inclk1
Block
8
÷C1
÷C2
÷C3
VCOOVRR
VCOUNDR
÷C4
PLL
output
mux
lock
÷n
clkswitch
clkbad0
clkbad1
activeclock
PFD
CP
LF
VCO
÷2
(2)
8
GCLKs
External clock
output
GCLK
(3)
VCO
Range
Detector
pfdena
÷M
no compensation;
ZDB mode
source-synchronous;
normal mode
GCLK
networks
Notes to
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) This is the VCO post-scale counter K.
(3) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another
PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.
1
The VCO post-scale counter K is used to divide the supported VCO range by two. The
VCO frequency reported by the Quartus II software in the PLL summary section of
the compilation report takes into consideration the VCO post-scale counter value.
Therefore, if the VCO post-scale counter has a value of 2, the frequency reported is
lower than the f
VCO
specification specified in the
and
chapters.
External Clock Outputs
Each PLL of the Cyclone III device family supports one single-ended clock output or
one differential clock output. Only the C0 output counter can feed the dedicated
external clock outputs, as shown in
without going through the GCLK.
Other output counters can feed other I/O pins through the GCLK.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
