Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLLs in the Cyclone III Device Family
5–9
Altera recommends using the
clkena
signals when switching the clock source to the
PLLs or the GCLK. The recommended sequence is:
1. Disable the primary output clock by deasserting the
clkena
signal.
2. Switch to the secondary clock using the dynamic select signals of the clock control
block.
3. Allow some clock cycles of the secondary clock to pass before reasserting the
clkena
signal. The exact number of clock cycles you must wait before enabling the
secondary clock is design-dependent. You can build custom logic to ensure glitch-
free transition when switching between different clock sources.
PLLs in the Cyclone III Device Family
The Cyclone III device family offers up to four PLLs that provide robust clock
management and synthesis for device clock management, external system clock
management, and high-speed I/O interfaces.
f
For more information about the number of PLLs in each device density, refer to the
chapter.
The Cyclone III device family PLLs have the same core analog structure.
lists the features available in the Cyclone III device family PLLs.
Table 5–3. Cyclone III Device Family PLL Hardware Features
Hardware Features
C (output counters)
M, N, C counter sizes
Dedicated clock outputs
Clock input pins
Spread-spectrum input clock tracking
PLL cascading
Compensation modes
Phase shift resolution
Programmable duty cycle
Output counter cascading
Input clock switchover
User mode reconfiguration
Loss of lock detection
Notes to
(1) C counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using a
non-50% duty cycle, the post-scale counters range from 1 through 256.
(2) Only applicable if the input clock jitter is in the input jitter tolerance specifications.
(3) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For
degree increments, the Cyclone III device family can shift all output frequencies in increments of at least 45°.
Smaller degree increments are possible depending on the frequency and divide parameters.
Availability
5
1 to 512
1 single-ended or 1 differential pair
4 single-ended or 2 differential pairs
v
Through GCLK
Source-Synchronous Mode, No Compensation
Mode, Normal Mode, and Zero Delay Buffer Mode
Down to 96-ps increments
v
v
v
v
v
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
