Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
5–5
shows the clock control block.
Figure 5–1. Clock Control Block
Clock Control Block
Internal Logic
DPCLK or CDPCLK
Static Clock Select
(3)
Enable/
Disable
Global
Clock
CLK[n + 3]
CLK[n + 2]
CLK[n + 1]
CLK[n]
C0
C1
inclk1
inclk0
f
IN
PLL
C2
C3
C4
CLKSWITCH
(1)
Static Clock
Select
(3)
CLKSELECT[1..0]
(2)
Internal Logic
(4)
Notes to
(1) The
clkswitch
signal can either be set through the configuration file or dynamically set when using the manual PLL switchover feature. The
output of the multiplexer is the input clock (f
IN
) for the PLL.
(2) The
clkselect[1..0]
signals are fed by internal logic and is used to dynamically select the clock source for the GCLK when the device is in user
mode.
(3) The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user mode is not feasible.
(4) You can use internal logic to enable or disable the GCLK in user mode.
Each PLL generates five clock outputs through the
c[4..0]
counters. Two of these
clocks can drive the GCLK through a clock control block, as shown in
f
For more information about how to use the clock control block in the Quartus
®
II
software, refer to the
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
