11–8
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Software Support
1
For Cyclone III LS devices, the “Enable
Open Drain on CRC Error Pin”
option is not
available because the Quartus II software sets the
CRC_ERROR
pin for the Cyclone III LS
device as open drain output by default.
Accessing Error Detection Block Through User Logic
The error detection circuit stores the computed 32-bit CRC signature in a 32-bit
register. This signature is read out by user logic from the core. The
<device>_crcblock
primitive is a WYSIWYG component used to establish the
interface from user logic to the error detection circuit. The
<device>_crcblock
primitive atom contains the input and output ports that must be included in the atom.
To access the logic array, the
<device>_crcblock
WYSIWYG atom must be
inserted into your design.
shows the error detection block diagram in FPGA devices and shows the
interface that the WYSIWYG atom enables in your design.
Figure 11–3. Error Detection Block Diagram
80MHz
Internal Chip Oscillator
Clock Divider
(1 to 256 Factor)
VCC
CRC_ERROR
(Shown in BIDIR Mode)
Pre-Computed CRC
(Saved in the Option Register)
Error Detection
Logic
SRAM
Bits
CRC
Computation
SHIFTNLD
REGOUT
1
The user logic is affected by the soft error failure, thus reading out the 32-bit CRC
signature through the
regout
should not be relied upon to detect a soft error. You
should rely on the
CRC_ERROR
output signal itself, because this
CRC_ERROR
output
signal cannot be affected by a soft error.
To enable the
<device>_crcblock
WYSIWYG atom, you must name the atom for each
Cyclone III device family accordingly.
Cyclone III Device Handbook
Volume 1
LDSRC
cyclecomplete
CLK
Logic Array
December 2011 Altera Corporation
CRC_ERROR
ALTERA [ ALTERA CORPORATION ]
