欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP3C16Q144C6ES 参数 Datasheet PDF下载

EP3C16Q144C6ES图片预览
型号: EP3C16Q144C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7308 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP3C16Q144C6ES的Datasheet PDF文件第239页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第240页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第241页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第242页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第244页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第245页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第246页浏览型号EP3C16Q144C6ES的Datasheet PDF文件第247页  
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Remote System Upgrade
9–85
1
To ensure the successful reconfiguration between the pages, assert
RU_nCONFIG
signal
for a minimum of 250 ns. This is equivalent to strobing the
reconfig
input of the
ALTREMOTE_UPDATE megafunction high for a minimum of 250 ns.
If there is an error or reconfiguration trigger condition, the remote system upgrade
state machine directs the system to load a factory or application configuration (based
on mode and error condition) by setting the control register accordingly.
lists the contents of the control register after such an event occurs for all
possible error or trigger conditions.
The remote system upgrade status register is updated by the dedicated error
monitoring circuitry after an error condition but before the factory configuration is
loaded.
Table 9–30. Control Register Contents After an Error or Reconfiguration Trigger Condition
Reconfiguration
Error/Trigger
nCONFIG
reset
nSTATUS
error
CORE triggered reconfiguration
CRC error
Wd time out
Control Register Setting In
Remote Update
All bits are 0
All bits are 0
Update register
All bits are 0
All bits are 0
User Watchdog Timer
The user watchdog timer prevents a faulty application configuration from stalling the
device indefinitely. The system uses the timer to detect functional errors after an
application configuration is successfully loaded into the Cyclone III device family.
The user watchdog timer is a counter that counts down from the initial value loaded
into the remote system upgrade control register by the factory configuration. The
counter is 29-bits wide and has a maximum count value of 2
29
. When specifying the
user watchdog timer value, specify only the most significant 12 bits. Remote system
upgrade circuitry appends 17’b1000 to form the 29 bits value for the watchdog timer.
The granularity of the timer setting is 2
17
cycles. The cycle time is based on the
frequency of the 10-MHz internal oscillator.
lists the operating range of the 10-MHz internal oscillator.
Table 9–31. 10-MHz Internal Oscillator Specifications
Minimum
5
Typical
6.5
Maximum
10
Unit
MHz
The user watchdog timer begins counting after the application configuration enters
device user mode. This timer must be periodically reloaded or reset by the application
configuration before the timer expires by asserting
RU_nRSTIMER.
If the application
configuration does not reload the user watchdog timer before the count expires, a
time-out signal is generated by the remote system upgrade dedicated circuitry. The
time-out signal tells the remote system upgrade circuitry to set the user watchdog
timer status bit (Wd) in the remote system upgrade status register and reconfigures the
device by loading the factory configuration.
August 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1