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EP3C16Q144C6ES 参数 Datasheet PDF下载

EP3C16Q144C6ES图片预览
型号: EP3C16Q144C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7308 K
品牌: ALTERA [ ALTERA CORPORATION ]
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9–82
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Remote System Upgrade
The control register bit positions are shown in
and listed in
In
the figure, the numbers show the bit position of a setting in a register. For example, bit
number 35 is the enable bit for the watchdog timer.
Figure 9–36. Remote System Upgrade Control Register
38
Rsv2
37
36
35
34 33
12 11
0
Cd_early Osc_int Wd_en Rsv1 Ru_address[21..0] Wd_timer[11..
When enabled, the early
CONF_DONE
check (Cd_early) option bit ensures that there is a
valid configuration at the boot address specified by the factory configuration and that
it is of the proper size. If an invalid configuration is detected or
CONF_DONE
pin is
asserted too early, the device resets and then reconfigures the factory configuration
image. The internal oscillator, as startup state machine clock (Osc_int) option bit,
ensures a functional startup clock to eliminate the hanging of startup when enabled.
When all option bits are turned on, they provide complete coverage for the
programming and startup portions of the application configuration. It is strongly
recommended that you turn on both the
Cd_early
and
Osc_int
option bits.
1
The
Cd_early
and
Osc_int
option bits for the application configuration must be
turned on by the factory configuration.
Table 9–27. Remote System Upgrade Control Register Contents
Control Register Bit
Wd_timer[11..0]
Value
12'b000000000000
Definition
User watchdog time-out value (most significant 12 bits of
29-bit count value:
{Wd_timer[11..0],17'b1000})
Ru_address[21..0]
Rsv1
Wd_en
Osc_int
Cd_early
Rsv2
Note to
Configuration address (most significant 22 bits of 24-bit
22'b0000000000000000000000 boot address value:
boot_address[23:0]
=
{Ru_address[21..0],2'b0})
1'b0
1'b1
1’b1
1’b1
1'b1
Reserved bit
User watchdog timer enable bit
Internal oscillator as startup state machine clock enable bit
Early
CONF_DONE
check
Reserved bit
(1) Option bit for the application configuration.
Remote System Upgrade Status Register
The remote system upgrade status register specifies the reconfiguration trigger
condition. The various trigger and error conditions include:
Cyclical redundancy check (CRC) error during application configuration
nSTATUS
assertion by an external device due to an error
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation