Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–67
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 2 of 4)
Pin Name
User
Mode
Configuration
Scheme
Pin Type
Description
Active-low chip enable. The
nCE
pin activates the Cyclone III
device family with a low signal to allow configuration. The
nCE
pin must be held low during configuration, initialization,
and user-mode. In a single-device configuration, it must be
tied low. In a multi-device configuration,
nCE
of the first
device is tied low while its
nCEO
pin is connected to the
nCE
pin of the next device in the chain. The
nCE
pin must also be
held low for successful JTAG programming of the device.
Output that drives low when configuration is complete. In a
single-device configuration, you can leave this pin floating or
use it as a user I/O pin after configuration. In a multi-device
configuration, this pin feeds the
nCE
pin of the next device.
The
nCEO
of the last device in the chain is left floating or is
used as a user I/O pin after configuration.
If you use the
nCEO
pin to feed the
nCE
pin of the next device,
use an external 10-k pull-up resistor to pull the
nCEO
pin
high to the V
CCIO
voltage of its I/O bank to help the internal
weak pull-up resistor.
If you use the
nCEO
pin as a user I/O pin after configuration,
set the state of the pin on the
Dual-Purpose Pin
settings.
Output control signal from the Cyclone III device family to the
serial configuration device in AS mode that enables the
configuration device. This pin functions as the
nCSO
pin in AS
mode and the
FLASH_NCE
pin in AP mode.
I/O
AS, AP
nCE
N/A
All
Input
nCEO
N/A if
option is
on. I/O if
option is
off.
All
Output open
drain
FLASH_nCE,
nCSO
Output
Output control signal from the Cyclone III device to the
parallel flash in AP mode that enables the flash. Connects to
the
CE#
pin on the Micron P30 or P33 flash.
This pin has an internal pull-up resistor that is always active.
In PS and FPP configuration,
DCLK
is the clock input used to
clock data from an external source into the target Cyclone III
device family. Data is latched into the device on the rising
edge of
DCLK.
In AS mode,
DCLK
is an output from the Cyclone III device
family that provides timing for the configuration interface, it
has an internal pull-up resistor (typically 25 k) that is
always active.
DCLK
N/A
PS, FPP, AS,
AP
Input (PS,
FPP). Output In AP mode,
DCLK
is an output from the Cyclone III device
(AS, AP
) that provides timing for the configuration interface.
In active configuration schemes (AS or AP), this pin will be
driven into an inactive state after configuration completes.
Alternatively, in active schemes, you can use this pin as a
user I/O during user mode. In passive schemes (PS or FPP)
that use a control host,
DCLK
must be driven either high or
low, whichever is more convenient. In passive schemes, you
cannot use
DCLK
as a user I/O in user mode. Toggling this pin
after configuration does not affect the configured device
August 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
