Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–51
Figure 9–25. JTAG Configuration of a Single Device Using a Download Cable (1.5-V or 1.8-V V
CCIO
Powering the JTAG Pins)
V
CCIO
V
CCIO
(2)
V
CCIO
(2)
(1)
V
CCIO
10 kΩ
Cyclone III Device Family
nCE
(3)
GND
N.C.
(4)
nCEO
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
DATA[0]
DCLK
TMS
TDI
TCK
TDO
(1)
10 kΩ
(5)
(5)
(5)
(5)
Download Cable
10-Pin Male Header (Top View)
Pin 1
V
CCIO
(6)
GND
V
IO
(7)
1 kΩ
GND
GND
Notes to
(1) The resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your
setup.
(2) Connect these pull-up resistors to the V
CCIO
supply of the bank in which the pin resides.
(3) The
nCE
must be connected to GND or driven low for successful JTAG configuration.
(4) The
nCEO
pin is left unconnected or used as a user I/O pin when it does not feed the
nCE
pin of another device.
(5) Connect the
nCONFIG
and
MSEL[3..0]
pins to support a non-JTAG configuration scheme. If you only use a JTAG
configuration, connect the
nCONFIG
pin to logic-high and the
MSEL[3..0]
pins to ground. In addition, pull
DCLK
and
DATA[0]
either high or low, whichever is convenient on your board.
(6) Power up the V
CC
of the ByteBlaster II, USB-Blaster, or Ethernet Blaster cable with supply from V
CCIO
. The
ByteBlaster II, USB-Blaster, and Ethernet Blaster cables do not support a target supply voltage of 1.2 V. For the target
supply voltage value, refer to the
and
(7) In the USB-Blaster and ByteBlaster II cables, this pin is connected to
nCE
when it is used for AS programming;
otherwise it is a no connect.
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the
TDI
pin to the
TDO
pin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the
TDO
pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration upon completion. At
the end of configuration, the software checks the state of
CONF_DONE
through the JTAG
port. When the Quartus II software generates a
.jam
for a multi-device chain, it
contains instructions to have all devices in the chain initialize at the same time. If
CONF_DONE
is not high, the Quartus II software indicates that configuration has failed.
If
CONF_DONE
is high, the software indicates that configuration was successful. After
the configuration bitstream is serially sent using the JTAG
TDI
port, the
TCK
port
clocks an additional clock cycle to perform device initialization.
August 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
